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blackfin and the blackfi n logo are registered tradem arks of analog devices, inc. blackfin embedded processor ADSP-BF539 / ADSP-BF539f rev. f document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 ?2013 analog devices, inc. all rights reserved. technical support www.analog.com features up to 533 mhz high performance blackfin processor two 16-bit macs, two 40-bit alus, four 8-bit video alus, 40-bit shifter risc-like register and instruction model for ease of programming and compil er friendly support advanced debug, trace, an d performance monitoring wide range of operating voltages; see operating conditions on page 26 qualified for automotive applications programmable on-chip voltage regulator 316-ball pb-free csp_bga package memory 148k bytes of on-chip memory 16k bytes of instruction sram/cache 64k bytes of instruction sram 32k bytes of data sram 32k bytes of data sram/cache 4k bytes of scratchpad sram optional 8m bit parallel flash with boot option memory management unit providing memory protection external memory controller with glueless support for sdram, sram, flash, and rom flexible memory booting opti ons from spi and external memory peripherals parallel peripheral interface (ppi), supporting itu-r 656 video data formats 4 dual-channel, full -duplex synchronous serial ports, supporting 16 stereo i 2 s channels 2 dma controllers supporting 26 peripheral dmas 4 memory-to-memory dmas controller area network (can) 2.0b controller media transceiver (mxvr) for connection to a most network 3 spi-compatible ports three 32-bit timer/counters with pwm support 3 uarts with support for irda 2 twi controllers compatible with i 2 c industry standard up to 38 general-purpose i/o pins (gpio) up to 16 general-purpose flag pins (gpf) real-time clock, watchdog timer, and 32-bit core timer on-chip pll capable of frequency multiplication debug/jtag interface figure 1. function al block diagram uart0 sport0-1 watchdog timer rtc spi0 timer0-2 ppi spi1-2 sport2-3 uart1-2 gpio port f gpio port d gpio port c gpio port e external port flash, sdram control boot rom jtag test and emulation voltage regulator dma controller 0 l1 instruction memory l1 data memory dma controller1 interrupt controller peripheral access bus d ma a c c e s s bu s 0 dma core bus 0 dma external bus 1 p e r ip h e ra la c c es s b u s twi0-1 can 2.0b mxvr 8m bit parallel flash (see table 1) d m a a c ce s s bu s 1 dma core bus 1 dma external bus 0 dma core bus 2 16 b
rev. f | page 2 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f table of contents features ................................................................. 1 memory ................................................................ 1 peripherals ............................................................. 1 general description ................................................. 3 low power architecture ......................................... 3 system integration ................................................ 3 ADSP-BF539/ADSP-BF539f processor peripherals ....... 3 blackfin processor core .......................................... 4 memory architecture ............................................ 5 dma controllers .................................................. 8 real-time clock ................................................... 9 watchdog timer .................................................. 9 timers ............................................................... 9 serial ports (sports) .......................................... 10 serial peripheral interface (spi) ports ...................... 10 2-wire interface ................................................. 10 uart ports ...................................................... 10 programmable i/o pins ........................................ 11 parallel peripheral interface ................................... 12 controller area network (can) interface ................ 12 media transceiver mac layer (mxvr) ................... 13 dynamic power management ................................ 13 voltage regulation .............................................. 15 clock signals ..................................................... 15 booting modes ................................................... 16 instruction set description .................................... 17 development tools .............................................. 17 example connections and layout considerations ....... 18 mxvr board layout guidelines ............................. 18 voltage regulator layout guidelines ....................... 19 additional information ........................................ 20 related signal chains ........................................... 20 pin descriptions .................................................... 21 specifications ........................................................ 26 operating conditions ........................................... 26 electrical characteristics ....................................... 27 absolute maximum ratings ................................... 30 esd sensitivity ................................................... 30 package information ............................................ 30 timing specifications ........................................... 31 output drive currents ......................................... 50 test conditions .................................................. 52 thermal characteristics ........................................ 55 316-ball csp_bga ball assignment .. ......................... 56 outline dimensions ................................................ 59 surface-mount design .......................................... 59 ordering guide ..................................................... 60 revision history 10/13rev. e to rev. f updated development tools .................................... 17 added notes to table 32 in serial portsenable and three-state .......................... 43 added timer clock timing ...................................... 48 revised timer cycle timing ..................................... 48 to view product/process change notifications (pcns) related to this data sheet revision, please visit the processors product page on the www.analog.com website and use the view pcn link.
ADSP-BF539 / ADSP-BF539f rev. f | page 3 of 60 | october 2013 general description the ADSP-BF539/ADSP-BF539f pr ocessors are members of the blackfin ? family of products, incorporating the analog devices, inc./intel micro signal architecture (msa). blackfin processors combine a dual-mac, state-of-the-art signal pro- cessing engine, the advantages of a clean, orthogonal risc-like microprocessor instruction set, and single-instruction, multi- ple-data (simd) multimedia capabilities into a single instruction set architecture. the ADSP-BF539/ADSP-BF539f pr ocessors are completely code compatible with other blackfin processors, differing only with respect to performance, pe ripherals, and on-chip memory. these features are shown in table 1 . by integrating a rich set of indu stry-leading system peripherals and memory, blackfin processors are the platform of choice for next generation applications that require risc-like program- mability, multimedia support , and leading edge signal processing in one integrated package. low power architecture blackfin processors provide wo rld class power management and performance. blackfin processors are designed in a low power and low voltage design methodology and feature dynamic power management, the ability to vary both the voltage and fre- quency of operation to sign ificantly lower overall power consumption. varying the voltage and frequency can result in a substantial reduction in power consumption, compared with simply varying the frequency of op eration. this translates into longer battery life and lower heat dissipation. system integration the ADSP-BF539/ADSP-BF539f pr ocessors are highly inte- grated system-on-a-ch ip solutions for the next generation of industrial and automotive applications including audio and video signal processing. by combining advanced memory con- figurations, such as on-chip flash memory, with industry- standard interfaces with a high performance signal processing core, users can develop cost-effe ctive solutions quickly without the need for costly external co mponents. the system peripherals include a most network media transceiver (mxvr), three uart ports, three spi ports, fo ur serial ports (sport), one can interface, two 2-wire interf aces (twi), four general-pur- pose timers (three with pwm capability), a real-time clock, a watchdog timer, a parallel periph eral interface, general-purpose i/o, and general-purpose flag pins. ADSP-BF539/ADSP-BF539f processor peripherals the ADSP-BF539/ADSP-BF539f proc essors contai n a rich set of peripherals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see figure 1 on page 1 ). the general-purpose peripheral s include functions such as uart, timers with pwm (pulse-width modulation) and pulse measurement capability, general-purpose flag i/o pins, a real- time clock, and a watchdog timer. this set of functions satisfies a wide variety of typical system support needs and is augmented by the system expansion capabilities of the device. in addition to these general-purpose peripherals, the processors contain high speed serial and parallel ports fo r interfacing to a variety of audio, video, and modem codec functions. an mxvr trans- ceiver transmits and receives audio and video data and control information on a most automotive multimedia network. a can 2.0b controller is provided for automotive control net- works. an interrupt controller manages interrupts from the on- chip peripherals or external sources. and power management control functions tailor the pe rformance and power characteris- tics of the processor and system to many application scenarios. all of the peripherals, gpio, can, twi, real-time clock, and timers, are supported by a flexible dma structure. there are also four separate memory dma channels dedicated to data transfers between the processo rs various memory spaces, including external sdram and asynchronous memory. multi- ple on-chip buses running at up to 133 mhz provide enough bandwidth to keep the processor core running along with activ- ity on all of the on-chip and external peripherals. the ADSP-BF539/ADSP-BF539f proc essors include an on-chip voltage regulator in support of the processors dynamic power management capability. the volt age regulator provides a range of core voltage levels from v ddext . the voltage regulator can be bypassed at the user's discretion. table 1. processor features feature ADSP-BF539 ADSP-BF539f8 sports 4 4 uarts 3 3 spi 3 3 twi 2 2 can 1 1 mxvr 1 1 ppi 1 1 internal 8m bit parallel flash 1 instruction sram/cache 16k bytes 16k bytes instruction sram 64k bytes 64k bytes data sram/cache 32k bytes 32k bytes data sram 32k bytes 32k bytes scratchpad 4k bytes 4k bytes maximum frequency 533 mhz 1066 mmacs 533 mhz 1066 mmacs package option bc-316 bc-316
rev. f | page 4 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f blackfin processor core as shown in figure 2 , the blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit alus, four video alus, and a 40-bit shifter. the computation units process 8-bit, 16-bit, or 32-bit data from the register file. the compute register file contai ns eight 32-bit registers. when performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. all operands for compute operations come from the multiported register file and instruction constant fields. each mac can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. signed and unsigned formats, rounding, and saturation are supported. the alus perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. in addition, many special instructions are included to acce lerate various signal processing tasks. these include bit operations such as field extract and pop- ulation count, modulo 2 32 multiply, divide primitives, saturation and rounding, and sign/exponent detection. the set of video instructions include byte alignment and packing operations 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute va lue/accumulate (saa) opera- tions. also provided are the co mpare/select and vector search instructions. for certain instructions, two 16-bit alu operations can be per- formed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute regi ster). by also using the second alu, quad 16-bit operations are possible. the 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. the program sequencer controls the flow of instruction execu- tion, including instruction alignment and decoding. for program flow control, the sequ encer supports pc relative and indirect conditional jumps (with static branch prediction), and subroutine calls. hardware is pr ovided to support zero over- head looping. the architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. figure 2. blackfin processor core sequencer align decode loop buffer 16 16 8 888 40 40 a0 a1 barrel shifter data arithmetic unit control unit r7.h r6.h r5.h r4.h r3.h r2.h r1.h r0.h r7.l r6.l r5.l r4.l r3.l r2.l r1.l r0.l astat 40 40 32 32 32 32 32 32 32 ld0 ld1 sd dag0 dag1 address arithmetic unit i3 i2 i1 i0 l3 l2 l1 l0 b3 b2 b1 b0 m3 m2 m1 m0 sp fp p5 p4 p3 p2 p1 p0 da1 da0 32 32 32 preg rab 32 to memory
ADSP-BF539 / ADSP-BF539f rev. f | page 5 of 60 | october 2013 the address arithmetic unit prov ides two addresses for simulta- neous dual fetches from memory. it contains a multiported register file consisti ng of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer regist ers (for c-style indexed stack manipulation). blackfin processors support a modified harvard architecture in combination with a hierarchical memory structure. level 1 (l1) memories are those that typically operate at the full processor speed with little or no latency. at the l1 level, the instruction memory holds instructions only. the two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. in addition, multiple l1 memory blocks are provided, offering a configurable mix of sram and cache. the memory manage- ment unit (mmu) provides memo ry protection for individual tasks that can be operating on the core and can protect system registers from unintended access. the architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. user mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and co re resources. the blackfin processor instruct ion set has been optimized so that 16-bit opcodes represent the most frequently used instruc- tions, resulting in excellent co mpiled code density. complex dsp instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. blackfin processors support a limited multi-issue ca pability, where a 32-bit instruc- tion can be issued in parallel with two 16-bit instructions, allowing the programmer to use ma ny of the core resources in a single instruction cycle. the blackfin processor assembly language uses an algebraic syn- tax for ease of coding and readability. the architecture has been optimized for use in conjunction with the c/c++ compiler, resulting in fast and effici ent software implementations. memory architecture the ADSP-BF539/ADSP-BF539f proc essors view memory as a single unified 4g byte address sp ace, using 32-bit addresses. all resources, including internal memory, external memory, and i/o control registers, occupy sepa rate sections of this common address space. the me mory portions of th is address space are arranged in a hierarchical structure to provide a good cost/per- formance balance of some ve ry fast, low latency on-chip memory as cache or sram, and larger, lower cost and perfor- mance off-chip memory systems. see figure 3 . the l1 memory system is th e primary highest performance memory available to the blackfin processor. the off-chip mem- ory system, accessed through the external bus interface unit (ebiu), provides expansion wi th sdram, flash memory, and sram, optionally accessing up to 132m bytes of physical memory. the memory dma controller provides high bandwidth data movement capability. it performs bl ock transfers of code or data between the internal memory an d the external memory spaces. internal (on-chip) memory the ADSP-BF539/ADSP-BF539f processor has three blocks of on-chip memory, providing high bandwidth access to the core. the first is the l1 instruction memory, consisting of 80k bytes sram, of which 16k bytes can be configured as a four-way set- associative cache. this memory is accessed at full processor speed. the second on-chip memory block is the l1 data memory, con- sisting of two banks of up to 32k bytes each . each memory bank is configurable, offering both cache and sram functionality. this memory block is accessed at full processor speed. the third memory block is a 4k byte scratch pad sram, which runs at the same speed as the l1 memories, but is only accessible as data sram and cannot be configured as cache memory. external (off-chip) memory external memory is accessed via the ebiu. this 16-bit interface provides a glueless connection to a bank of synchronous dram (sdram) as well as up to four banks of asynchronous memory devices including flash, epro m, rom, sram, and memory mapped i/o devices. figure 3. ADSP-BF539/ADSP-BF539f internal/external memory map reserved core mmr registers (2m bytes) reserved scratchpad sram (4k bytes) instruction sram (64k bytes) system mmr registers (2m bytes) reserved reserved data bank b sram / cache (16k bytes) data bank b sram (16k bytes) data bank a sram / cache (16k bytes) async memory bank 3 (1m bytes) or on-chip flash (ADSP-BF539f only) async memory bank 2 (1m bytes) or on-chip flash (ADSP-BF539f only) async memory bank 1 (1m bytes) or on-chip flash (ADSP-BF539f only) async memory bank 0 (1m bytes) or on-chip flash (ADSP-BF539f only) sdram memory (16m bytes to 128m bytes) instruction sram / cache (16k bytes) i n t e rn a l m e m o r y m a p e xt e r n a l m e m or y m a p 0xffff ffff 0xffe0 0000 0xffb0 0000 0xffa1 4000 0xffa1 0000 0xff90 8000 0xff90 4000 0xff80 8000 0xff80 4000 0xef00 0000 0x2040 0000 0x2030 0000 0x2020 0000 0x2010 0000 0x2000 0000 0x0800 0000 0x0000 0000 0xffc0 0000 0xffb0 1000 0xffa0 0000 reserved reserved data bank a sram (16k bytes) 0xff90 0000 0xff80 0000 reserve d
rev. f | page 6 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f the pc133-compliant sdram cont roller can be programmed to interface to up to 128m by tes of sdram. the sdram con- troller allows one row to be open for each internal sdram bank, for up to four internal sdram banks, improving overall system performance. the asynchronous memory cont roller can be programmed to control up to four banks of devices with very flexible timing parameters for a wide variety of devices. each bank occupies a 1m byte segment regardless of th e size of the devices used, so that these banks will only be cont iguous if each is fully popu- lated with 1m byte of memory. flash memory (ADSP-BF539f only) the ADSP-BF539f8 processor contains a separate flash die, connected to the ebiu bus, within the package of the processor. figure 4 shows how the flash memory die and blackfin proces- sor die are connected. the ADSP-BF539f8 contains an 8m bit (512k 16-bit) bottom boot sector spansion s29al008j known good die flash memory. additional information for this product can be found in the spansion data sheet at www.spansion.com . features include the following: ? access times as fast as 70 ns (ebiu registers must be set appropriately) ? sector protection ? one million write cycles per sector ? 20 year data retention the blackfin processo r connects to the flash memory die with address, data, chip enable, write enable, and output enable con- trols as if it were an external memory device. note that the write-protect input pin to the flash is not connected and inac- cessible, disabling this feature. the flash chip enable pin fce must be connected to ams0 or ams3C1 through a printed circuit board trace. when connected to ams0 , the blackfin processor can boot from the flash die. when connected to ams3C1 , the flash memory appears as non- volatile memory in the processor memory map, shown in figure 3 . flash memory programming the ADSP-BF539f8 flash memory can be programmed before or after mounting on the printed circuit board. to program the flash prior to mounting on the printed circuit board, use a hardware programm ing tool that can provide the data, address, and control stimuli to the flash die through the external pins on the package. during this programming, v ddext and gnd must be provided to the package and the blackfin must be held in rese t with bus request (br ) asserted and a clkin provided. the visualdsp++ tools can be used to program the flash mem- ory after the device is mounted on a printed circuit board. flash memory sector protection to use the sector protection feature, a high voltage (+8.5 v to +12.5 v) must be applied to the flash freset pin. refer to the flash data sheet for details. i/o memory space blackfin processors do not defi ne a separate i/o space. all resources are mapped through the flat 32-bit address space. on- chip i/o devices have their co ntrol registers mapped into mem- ory mapped registers (mmrs) at addresses near the top of the 4g byte address space. these are separated into two smaller blocks, one of which contains the control mmrs for all core functions, and the other of which contains the registers needed for setup and control of the on-chip peripherals outside of the core. the mmrs are accessible only in supervisor mode and appear as reserved spac e to on-chip peripherals. booting the ADSP-BF539/ADSP-BF539f pr ocessors contain a small boot kernel, which configures the appropriate peripheral for booting. if the processors are configured to boot from boot rom memory space, they start executing from the on-chip boot rom. for more information, see booting modes on page 16 . event handling the event controller handles all asynchronous and synchronous events to the processor. the pr ocessors provide event handling that supports both nesting and prioritization. nesting allows multiple event service routines to be active simultaneously. pri- oritization ensures that servicing of a higher priority event takes precedence over servicing of a lo wer priority event. the control- ler provides support for five different types of events: ? emulation C an emulation ev ent causes the processor to enter emulation mode, allowing command and control of the processor via the jtag interface. ? reset C this event resets the processor. figure 4. internal connection of flash memory (ADSP-BF539f8) vss freset fce reset data15 - 0 gnd vddext addr19 - are awe gnd data15 - 0 ardy awe vcc byte reset ce ams3 - 0 reset are ardy addr19 - 1 oe we ry/ by v ddext ADSP-BF539f package b s29al008j flash die ams3 - 0 dq15 - 0 a18 - 0 wp nc
ADSP-BF539 / ADSP-BF539f rev. f | page 7 of 60 | october 2013 ? nonmaskable interrupt (nmi ) C the nmi event can be generated by the software watchdog timer or by the nmi input signal to the processor. the nmi event is frequently used as a power-down indicator to initiate an orderly shut- down of the system. ? exceptions C events that occur synchronously to program flow (i.e., the exception will be taken before the instruction is allowed to complete). conditions such as data alignment violations and undefined instructions cause exceptions. ? interrupts C events that occur asynchronously to program flow. they are caused by in put pins, timers, and other peripherals, as well as by an explicit software instruction. each event type has an associated register to hold the return address and an associated return-from-event instruction. when an event is triggered, the state of the processor is saved on the supervisor stack. the ADSP-BF539/ADSP-BF539f pr ocessors event controller consists of two stages, the core event controller (cec) and the system interrupt controller (sic). the core event controller works with the system interrupt controller to prioritize and con- trol all system events. concep tually, interrupts from the peripherals enter into the sic and are then routed directly into the general-purpose interrupts of the cec. core event controller (cec) the cec supports nine general-purpose interrupts (ivg15C7), in addition to the dedicated interrupt and exception events. of these general-purpose interrupts, the two lowest priority inter- rupts (ivg15C14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the processors peripherals. table 2 describes the inputs to the cec, identifies their names in the event vector table (evt), and lists their priorities. system interrupt controller (sic) the system interrupt controller (sic) provides the mapping and routing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the cec. although the ADSP-BF539/adsp- bf539f processo rs provide a default mapping, the user can alter the mappings and priorities of interrupt events by writing th e appropriate values into the interrupt assignment registers (sic_iarx). table 3 describes the inputs into the sic and the default mappings into the cec. event control the ADSP-BF539/ADSP-BF539f pr ocessors provide the user with a very flexible mechanism to control the processing of events. in the cec, three registers are used to coordinate and control events. each regi ster is 32 bits wide: ? cec interrupt latch register (ilat) C the ilat register indicates when events have been latched. the appropriate bit is set when the processor has latched the event and is cleared when the event has been accepted into the system. this register is updated automatically by the controller, but it can also be written to clear (cancel) latched events. this register may be read while in supervisor mode and may only be written while in supe rvisor mode when the corre- sponding imask bit is cleared. ? cec interrupt mask register (imask) C the imask regis- ter controls the masking and unmasking of individual events. when a bit is set in the imask register, that event is unmasked and will be processe d by the cec when asserted. a cleared bit in the imask register masks the event, preventing the processor fr om servicing the event even though the event can be latched in the ilat register. this register can be read or written while in supervisor mode. general-purpose interrupts ca n be globally enabled and disabled with the sti and cl i instructions, respectively. ? cec interrupt pending register (ipend) C the ipend register keeps track of all ne sted events. a set bit in the ipend register indicates whet her the event is currently active or nested at some level. this register is updated auto- matically by the controller but can be read while in supervisor mode. the sic allows further control of event processing by providing three 32-bit interrupt control and st atus registers. each register contains a bit correspo nding to each of the peripheral interrupt events shown in table 3 on page 8 . ? sic interrupt mask register s (sic_imaskx) C these regis- ters control the masking and un masking of each peripheral interrupt event. when a bit is set in these registers, that peripheral event is unmasked and will be processed by the system when asserted . a cleared bit in th ese registers masks the peripheral event, preventi ng the processor from servic- ing the event. ? sic interrupt status register s (sic_isrx) C as multiple peripherals can be mapped to a single event, these registers allow the software to determ ine which peripheral event source triggered the interrupt. a set bit indicates that the peripheral is asserting the inte rrupt, and a cleared bit indi- cates that the peripheral is not asserting the event. ? sic interrupt wake-up enable registers (sic_iwrx) C by enabling the corresponding bit in these registers, a periph- eral can be configured to wake up the processor, should the core be idled or in sleep mode when the event is generated. ( for more information, see dynamic power management on page 13. ) because multiple interrupt source s can map to a single general- purpose interrupt, multiple puls e assertions ca n occur simulta- neously, before or during interrupt processing for an interrupt event already detected on this interrupt input. the ipend reg- ister contents are monitored by the sic as the interrupt acknowledgement. the appropriate ilat register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). the bit is cleared when the respective ipend register bit is set. the ipend bit indicates that the event has entered into the proces- sor pipeline. at this point the cec will recognize and queue the next rising edge event on the corresponding event input. the minimum latency from the rising edge transition of the
rev. f | page 8 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f general-purpose interrupt to the ipend output asserted is three core clock cycles; however, the latency can be much higher, depending on the activity within and the state of the processor. dma controllers the processors have multiple , independent dma controllers that support automated data transfers with minimal overhead for the processor core. dma tr ansfers can occur between the ADSP-BF539/ADSP-BF539f proce ssor internal memories and any of its dma capable peripher als. additionally, dma trans- fers can be accomplished be tween any of the dma-capable peripherals and external devices connected to the external memory interfaces, including the sdram controller and the asynchronous memory controll er. dma capable peripherals include the sports, spi ports, uarts, and ppi. each individ- ual dma capable peripheral ha s at least one dedicated dma channel. in addition, the mxvr peripheral has its own dedi- cated dma controller, which supports its own unique set of operating modes. table 2. core event controller (cec) priority (0 is highest) event class evt entry 0emulation/test controlemu 1 reset rst 2 nonmaskable interrupt nmi 3exception evx 4 reserved 5 hardware error ivhw 6 core timer ivtmr 7 general interrupt 7 ivg7 8 general interrupt 8 ivg8 9 general interrupt 9 ivg9 10 general interrupt 10 ivg10 11 general interrupt 11 ivg11 12 general interrupt 12 ivg12 13 general interrupt 13 ivg13 14 general interrupt 14 ivg14 15 general interrupt 15 ivg15 table 3. system and core event mapping event source core event name pll wake-up interrupt ivg7 dma controller 0 error ivg7 dma controller 1 error ivg7 ppi error interrupt ivg7 sport0 error interrupt ivg7 sport1 error interrupt ivg7 sport2 error interrupt ivg7 sport3 error interrupt ivg7 mxvr synchronous data interrupt ivg7 spi0 error interrupt ivg7 spi1 error interrupt ivg7 spi2 error interrupt ivg7 uart0 error interrupt ivg7 uart1 error interrupt ivg7 uart2 error interrupt ivg7 can error interrupt ivg7 real-time clock interrupt ivg8 dma0 interrupt (ppi) ivg8 dma1 interrupt (sport0 rx) ivg9 dma2 interrupt (sport0 tx) ivg9 dma3 interrupt (sport1 rx) ivg9 dma4 interrupt (sport1 tx) ivg9 dma8 interrupt (sport2 rx) ivg9 dma9 interrupt (sport2 tx) ivg9 dma10 interrupt (sport3 rx) ivg9 dma11 interrupt (sport3 tx) ivg9 dma5 interrupt (spi0) ivg10 dma14 interrupt (spi1) ivg10 dma15 interrupt (spi2) ivg10 dma6 interrupt (uart0 rx) ivg10 dma7 interrupt (uart0 tx) ivg10 dma16 interrupt (uart1 rx) ivg10 dma17 interrupt (uart1 tx) ivg10 dma18 interrupt (uart2 rx) ivg10 dma19 interrupt (uart2 tx) ivg10 timer0, timer1, timer2 interrupts ivg11 twi0 interrupt ivg11 twi1 interrupt ivg11 can receive interrupt ivg11 can transmit interrupt ivg11 mxvr status interrupt ivg11 mxvr control message interrupt ivg11 mxvr asynchronous packet interrupt ivg11 programmable flags interrupts ivg12 mdma0 stream 0 interrupt ivg13 mdma0 stream 1 interrupt ivg13 mdma1 stream 0 interrupt ivg13 mdma1 stream 1 interrupt ivg13 software watchdog timer ivg13 table 3. system and core event mapping (continued) event source core event name
ADSP-BF539 / ADSP-BF539f rev. f | page 9 of 60 | october 2013 the dma controllers support both 1-dimensional (1-d) and 2-dimensional (2-d) dma transfer s. dma transfer initializa- tion can be implemented from registers or from sets of parameters called de scriptor blocks. the 2-d dma capability suppor ts arbitrary row and column sizes up to 64k elements by 64k elements and arbitrary row and column step sizes up to 32k elements. furthermore, the col- umn step size can be less than the row step size, allowing implementation of interleaved da ta streams. this feature is especially useful in video applications where data can be deinterleaved on the fly. examples of dma types support ed by the processors dma controller include: ? a single, linear buffer that stops upon completion ? a circular, auto-refreshing bu ffer that interrupts on each full or fractionally full buffer ? 1-d or 2-d dma using a linked list of descriptors ?2-d dma using an array of desc riptors, specifying only the base dma address wi thin a common page in addition to the dedicated peripheral dma channels, there are four memory dma channels prov ided for transfers between the various memories of the adsp -bf539/ADSP-BF539f processor system. this enables tr ansfers of blocks of data between any of the memoriesincluding external sdram, rom, sram, and flash memorywith minimal processor intervention. memory dma transfers can be controlled by a very flexible descriptor- based methodology or by a standard register-based autobuffer mechanism. real-time clock the ADSP-BF539/ADSP-BF539f processor real-time clock (rtc) provides a robust set of digital watch features, including current time, stopwatch, and alarm. the rtc is clocked by a 32.768 khz crystal external to the blackfin processors. the rtc peripheral has de dicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a low power state. the rtc provides several programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch count- down, or interrupt at a programmed alarm time. the 32.768 khz input clock frequency is divided down to a 1 hz signal by a prescaler. the counter function of the timer consists of four counters: a 60-second co unter, a 60-minute counter, a 24-hour counter, and an 32,768-day counter. when enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. there are two alarms: the first alarm is for a time of day. the second alarm is for a day and time of that day. the stopwatch function counts down from a programmed value, with one second resolu tion. when the stopwatch is enabled and the counter underflows, an interrupt is generated. like the other peripherals, the rtc can wake up the processor from sleep mode upon generati on of any rtc wake-up event. additionally, an rtc wake-up ev ent can wake up the processor from deep sleep mode, and wake up the on-chip internal voltage regulator from a powered down state. connect rtc pins rtxi and rtxo with external components as shown in figure 5 . watchdog timer the processors include a 32-bit timer that can be used to imple- ment a software watchdog function. a software watchdog can improve system availabi lity by forcing the processor to a known state through generation of a hardware reset, nonmaskable interrupt (nmi), or general-pu rpose interrupt, if the timer expires before being reset by so ftware. programs initialize the count value of the timer, enable the appropriate interrupt, and then enable the timer. thereafter , the software must reload the counter before it counts to ze ro from the programmed value. this protects the system from remaining in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. if configured to generate a hard ware reset, the watchdog timer resets both the core and the proc essor peripherals. after a reset, software can determine if the wa tchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register. the timer is clocked by the syst em clock (sclk), at a maximum frequency of f sclk . timers there are four general-purpose programmable timer units in the ADSP-BF539/ADSP-BF539f proc essors. three timers have an external pin that can be conf igured either as a pulse-width modulator (pwm) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. these timers can be synchronized to figure 5. external components for rtc rtxo c1 c2 x1 suggested components: ecliptek ec38j (through-hole package) epson mc405 12 pf load (surface-mount package) c1 = 22pf c2 = 22pf r1 = 10m : note: c1 and c2 are specific to crystal specified for x1. contact crystal manufacturer for details. c1 and c2 specifications assume board trace capacitance of 3pf. rtxi r1
rev. f | page 10 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f an external clock input to the pf1 pin (taclk), an external clock input to the ppi_clk pin (tmrclk), or to the internal sclk. the timer units can be used in conjunction with uart0 to measure the width of the pulses in the data stream to provide an auto-baud detect function for a serial channel. the timers can generate interrupt s to the processor core provid- ing periodic events for synchron ization, either to the system clock or to a count of external signals. in addition to the three general-purpose programmable timers, a fourth timer is also provided. th is extra timer is clocked by the internal processor clock and is typically used as a system tick clock for generation of operating system periodic interrupts. serial ports (sports) the ADSP-BF539/ADSP-BF539f pr ocessors incorporate four dual-channel synchronous serial ports for serial and multipro- cessor communications. the sp orts support the following features: ?i 2 s capable operation. ? bidirectional operation C each sport has two sets of inde- pendent transmit and receive pins, enabling 16 channels of i 2 s stereo audio. ? buffered (8-deep) transmit an d receive ports C each port has a data register for transfe rring data words to and from other processor components and shift registers for shifting data in and out of the data registers. ? clocking C each transmit and re ceive port can either use an external serial clock or generate its own, in frequencies ranging from (f sclk /131,070) hz to (f sclk /2) hz. ? word length C each sport supports serial data words from 3 bits to 32 bits in leng th, transferred mo st significant bit first or least significant bit first. ? framing C each transmit and receive port can run with or without frame sync signals for each data word. frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync. ? companding in hardware C each sport can perform a-law or -law companding according to itu recommen- dation g.711. companding can be selected on the transmit and/or receive channel of the sport without additional latencies. ? dma operations with single-cycle overhead C each sport can automatically receive and tr ansmit multiple buffers of memory data. the processor can link or chain sequences of dma transfers between a sport and memory. ? interrupts C each transmit a nd receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer or buffers through dma. ? multichannel capability C each sport supports 128 chan- nels out of a 1024-channel wind ow and is compatible with the h.100, h.110, mvip-90, and hmvip standards. serial peripheral interface (spi) ports the processors incorporate thr ee spi-compatible ports that enable the processor to commun icate with multiple spi com- patible devices. the spi interface uses three pins for transferring data: two data pins (master output-slave input, mosix, and master input-slave output, misox) and a clock pin (serial clock, sckx). an spi chip select input pin (spixss ) lets other spi devices select the processor. for spi0, seven spi chip select output pins (spi0- sel7C1 ) let the processor select other spi devices. spi1 and spi2 each have a single spi ch ip select output pin (spi1sel1 and spi2sel1 ) for spi point-to-point communication. each of the spi select pins is a reconfigured gpio pin. using these pins, the spi ports provide a full-duplex , synchronous serial interface, which supports both master/slave modes and multimaster environments. the spi ports baud rate and clock phase/polarities are pro- grammable, and they each have an integrated dma controller, configurable to support transmit or receive data streams. each spi dma controller can only serv ice unidirectional accesses at any given time. the spi port clock rate is calculated as: where the 16-bit spix_baud register contains a value of 2 to 65,535. during transfers, the spi port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. the serial clock line sy nchronizes the shifting and sam- pling of data on the two serial data lines. 2-wire interface the processors incorporate two 2-wire interface (twi) modules that are compatible with the philips inter-ic bus standard. the twi modules offer the capabilities of simultaneous master and slave operation, support for 7- bit addressing, and multimedia data arbitration. the twi also includes master clock synchroni- zation and support for clock low extension. the twi interface uses two pins for transferring clock (sclx) and data (sdax) and supports the protocol at speeds up to 400 kbps. the twi interface pins are comp atible with 5 v logic levels. uart ports the processors incorporate thr ee full-duplex universal asyn- chronous receiver/transmitter (u art) ports, which are fully compatible with pc standard uarts. the uart ports provide a simplified uart interface to other peripherals or hosts, sup- porting full-duplex, dma supported, asynchronous transfers of serial data. the uart ports incl ude support for 5 data bits to 8 data bits, 1 stop bit or 2 stop bits, and none, even, or odd par- ity. the uart ports support two modes of operation: spi clock rate f sclk 2spix_baud ? ----------------------------------- - =
ADSP-BF539 / ADSP-BF539f rev. f | page 11 of 60 | october 2013 ? pio (programmed i/o) C the processor sends or receives data by writing or reading i/o mapped uart registers. the data is double buffered on both transmit and receive. ? dma (direct memory access) C the dma controller trans- fers both transmit and receive data. this reduces the number and frequency of interr upts required to transfer data to and from memory. each uart has two dedicated dma channels, one for transmit and one for receive. these dma channels have lower default priority than most dma channels because of their re latively low service rates. each uart ports baud rate, seri al data format, error code gen- eration and status, and interrupts are programmable: ? supporting bit rates ranging from (f sclk /1,048,576) to (f sclk /16) bits per second. ? supporting data formats from 7 bits to 12 bits per frame. ? both transmit and receive oper ations can be configured to generate maskable interrupts to the processor. each uart ports clock rate is calculated as: where the 16-bit uart_divisor comes from the uartx_dlh register (most significant 8 bits ) and uartx_dll register (least significant 8 bits). in conjunction with the general-purpose timer functions, auto- baud detection is supported on uart0. the capabilities of the uarts are further extended with sup- port for the infrared data association (irda ? ) serial infrared physical layer link specification (sir) protocol. programmable i/o pins the ADSP-BF539/ADSP-BF539f processor has numerous peripherals that may no t all be required for every application. therefore, many of the pins ha ve a secondary function as pro- grammable i/o pins. there are tw o types of programmable i/o pins with slightly different functionality: programmable flags and general-purpose i/o. programmable flags (gpio port f) there are 16 bidirectional, gene ral-purpose programmable flag (pf15C0) pins on gpio port f. each programmable flag can be individually controlled by manipulation of th e flag control, sta- tus, and interrupt registers: ? flag direction control register C specifies the direction of each individual pfx pin as input or output. ? flag control and status register s C the processors employ a write one to modify mechan ism that allows any combi- nation of individual flags to be modified in a single instruction, without affecting the level of any other flags. four control registers are prov ided. one register is written in order to set flag values, one register is written in order to clear flag values, one register is written in order to toggle flag values, and one register is written in order to specify a flag value. reading the flag status register allows software to interrogate the sense of the flags. ? flag interrupt mask registers C the two flag interrupt mask registers allow each individual pfx pin to function as an interrupt to the processor. similar to the two flag control registers that are used to set and clear individual flag values, one flag interrupt mask register sets bits to enable interrupt function, and the other flag in terrupt mask register clears bits to disable interrupt function. pfx pins defined as inputs can be configured to generate hardware interrupts, while output pfx pins can be triggered by software interrupts. ? flag interrupt sensitivity registers C the two flag interrupt sensitivity registers specify wh ether individual pfx pins are level- or edge-sensitive an d specifyif edge-sensitive whether just the rising edge or both the rising and falling edges of the signal are signific ant. one register selects the type of sensitivity, and one re gister selects which edges are significant for edge-sensitivity. the pfx pins can also be used by the spi0 and ppi ports as shown in table 4 , depending on how the peripherals are config- ured. care must be taken so th at these pins are not used for multiple purposes simultaneously. general-purpose i/o ports c, d, and e there are 38 general-purpose i/o pins that are multiplexed with other peripherals. they are arrang ed into ports c, d, and e as shown in table 4 . the gpio differ fr om the programmable flags on port f in that the gpio pins cannot generate interrupts to the processor. the general-purpose i/o pins can be individually controlled by manipulation of the control and st atus registers. these pins will not cause interrupts to be generated to the processor but can be polled to determine their status. ? gpio direction control register C specifies the direction of each individual gpiox pin as input or output. ? gpio control and status regist ers C the processors employ a write one to modify mechanism that allows any combi- nation of individual gpio pins to be modified in a single uart clock rate f sclk 16 uart_divisor ? -------------------------------------------- = table 4. programmable flag/gpio ports peripheral alternate programmable flag/ gpio port function ppi pf15C3 sport2 pe7C0 sport3 pe15C8 spi0 pf7C0 spi1 pd4C0 spi2 pd9C5 uart1 pd11C10 uart2 pd13C12 can pc1C0 1 1 pc1 and pc4 are open-drain wh en configured as gpio outputs. mxvr pc9C4 1
rev. f | page 12 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f instruction, without affecting the level of any other gpio pin. four control registers and a data register are provided for each gpio port. one register is written in order to set gpio pin values, one register is written in order to clear gpio pin values, one register is written in order to toggle gpio pin values, and one regist er is written in order to specify a gpio input or output. reading the gpio data register allows software to determine the state of the input gpio pins. note that the gp pin is used to specify the status of the gpio pins pc9Cpc4 at power up. if gp is tied high, then pins pc9Cpc4 are configured as gpio after reset. the pins cannot be reconfigured through softwa re, and special care must be taken with the mlf pin. if the gp pin is tied low, then the pins are configured as mxvr pins after reset but can be reconfig- ured as gpio pins through software. parallel peripheral interface the ADSP-BF539/ADSP-BF539f pr ocessors provide a parallel peripheral interface (ppi) that can connect direct ly to parallel adc and dac converters, video encoders and decoders, and other general-purpose peripherals. the ppi consists of a dedi- cated input clock pin, up to 3 frame synchronization pins, and up to 16 data pins. the input cl ock supports parallel data rates up to f sclk /2 mhz, and the synchronization signals can be con- figured as either inputs or outputs. the ppi supports a variety of general-purpose and itu-r 656 modes of operation. in general-purpose mode, the ppi provides half-duplex, bidirectional data tr ansfer with up to 16 bits of data. up to 3 frame synchronization signals are also provided. in itu-r 656 mode, the ppi provides half-duplex, bidirectional transfer of 8- or 10-bit video da ta. additionally, on-chip decode of embedded start-of-line (sol ) and start-of-field (sof) pre- amble packets are supported. general-purpose mode descriptions the general-purpose modes of th e ppi are intended to suit a wide variety of data capture and transmission applications. three distinct submodes are supported: ? input mode C frame syncs and data are inputs into the ppi. ? frame capture mode C frame syncs are outputs from the ppi, but data are inputs. ? output mode C frame syncs and data are outputs from the ppi. input mode this mode is intended for adc applications, as well as video communication with hardware sign aling. in its simplest form, ppi_fs1 is an external frame sync input that controls when to read data. the ppi_delay mmr allows for a delay (in ppi_- clk cycles) between reception of this frame sync and the initiation of data reads. the nu mber of input data samples is user programmable and defined by the contents of the ppi_count register. the ppi supports 8-bit, and 10-bit through 16-bit data and are programmable in the ppi_con- trol register. frame capture mode this mode allows the video source(s) to act as a slave (e.g., for frame capture). the processors co ntrol when to read from the video source(s). ppi_fs1 is an hsync output, and ppi_fs2 is a vsync output. output mode this mode is used for transmitting video or other data with up to three output frame syncs. ty pically, a single frame sync is appropriate for data converter applications, whereas two or three frame syncs could be used for sending video with hard- ware signaling. itu-r 656 mode descriptions the itu-r 656 modes of the ppi are intended to suit a wide variety of video capture, proce ssing, and transmission applica- tions. three distinct submodes are supported: ?active video only mode ? vertical blanking only mode ? entire field mode active video only mode this mode is used when only th e active video portion of a field is of interest and not any of the blanking intervals. the ppi will not read in any data between the end of active video (eav) and start of active video (sav) preamb le symbols, or any data pres- ent during the vertical blanking intervals. in this mode, the control byte sequences are not stored to memory; they are filtered by the ppi. after synchronizing to the start of field 1, the ppi ignores incoming samples until it sees an sav code. the user specifies the number of acti ve video lines per frame (in the ppi_count register). vertical blanking interval mode in this mode, the ppi only transfers vertical blanking interval (vbi) data. entire field mode in this mode, the entire incoming bit stream is read in through the ppi. this includes active vide o, control preamble sequences, and ancillary data that can be embedded in horizontal and verti- cal blanking intervals. data transfer starts immediately after synchronization to field 1. controller area network (can) interface the ADSP-BF539/ADSP-BF539f processors provide a can controller that is a communicat ion controller implementing the controller area network (can) v2.0b protocol. this protocol is an asynchronous communications protocol used in both indus- trial and automotive control sy stems. can is well suited for control applications due to its ability to communicate reliably over a network since the protoc ol incorporates crc checking, message error tracking, and fault node confinement.
ADSP-BF539 / ADSP-BF539f rev. f | page 13 of 60 | october 2013 the can controller is based on a 32-entry mailbox ram and supports both the sta ndard and extended identifier (id) mes- sage formats specified in the can protocol specification, revision 2.0, part b. each mailbox consists of eight 16-bit data words. the data is divided into fields, which includes a message identifier, a time stamp, a byte count, up to 8 bytes of data, and several control bits. each node monitors the messages being passed on the net- work. if the identifier in the transmitted message matches an identifier in one of its mailboxe s, then the module knows that the message was meant for it, passe s the data into its appropriate mailbox, and signals the processo r of message arrival with an interrupt. the can controller can wake up the processor from sleep mode upon generation of a wake-up even t, such that the processor can be maintained in a low power mode during idle conditions. additionally, a can wake-up event can wake up the on-chip internal voltage regulator from the hibernate state. the electrical characteristics of each network connection are very stringent; therefore, the can interface is typically divided into two parts: a controller and a transceiver. this allows a sin- gle controller to support differ ent drivers and can networks. the ADSP-BF539/ADSP-BF539f ca n module represents the controller part of the interface. this modules network i/o is a single transmit output and a single receive input, which connect to a line transceiver. the can clock is derived from the processor system clock (sclk) through a programmable divider and therefore does not require an additional crystal. media transceiver mac layer (mxvr) the ADSP-BF539/ADSP-BF539f pr ocessors provide a media transceiver (mxvr) mac layer, allowing the processor to be connected directly to a most network through just an fot or electrical phy. the mxvr is fully compatible with industry standard standalone most controller de vices, supporting 22.579 mbps or 24.576 mbps data transfer. it o ffers faster lock times, greater jitter immunity, and a sophisticated dma scheme for data transfers. the high speed internal interface to the core and l1 memory allows the full bandwidth of the network to be utilized. the mxvr can operate as either the network master or as a net- work slave. synchronous data is transferre d to or from the synchronous data channels through eight pr ogrammable dma engines. the synchronous data dma engines ca n operate in various modes, including modes that trigger dma operation when data pat- terns are detected in the receiv e data stream. furthermore, two dma engines support asynchronous traffic and control mes- sage traffic. interrupts are generated when a user-defined amount of syn- chronous data has been sent or received by the processor or when asynchronous packets or co ntrol messages have been sent or received. the mxvr peripheral can wake up the processor from sleep mode when a wake-up preamble is received over the network or based on any other mxvr interrupt event. additionally, detec- tion of network activity by the mxvr can be used to wake up the processor from sleep mode and wake up the on-chip inter- nal voltage regulator from the powered-down hibernate state. these features allow the proce ssor to operate in a low-power state when there is no network activity or when data is not cur- rently being received or transmitted by the mxvr. the mxvr clock is provided thro ugh a dedicated external crys- tal or crystal oscillator. fo r 44.1 khz frame syncs, use a 45.1584 mhz crystal or oscillator; for 48 khz frame syncs, use a 49.152 mhz crystal or oscillator. if using a crystal to provide the mxvr clock, use a parallel- resonant, fundamental mode, microprocessor-grade crystal. dynamic power management the ADSP-BF539/ADSP-BF539f processors provide four oper- ating modes, each with a differe nt performance/power profile. in addition, dynamic power management provides the control functions to dynamically alter th e processor core supply voltage, further reducing power dissipation . control of clocking to each of the ADSP-BF539/ADSP-BF539f processor peripherals also reduces power consumption. see table 5 for a summary of the power settings for each mode. full-on operating modemaximum performance in the full-on mode, the pll is enabled and is not bypassed, providing capability for maximum operational frequency. this is the power-up default execut ion state in which maximum per- formance can be achieved. the processor core and all enabled peripherals run at full speed. active operating modemoderate dynamic power savings in the active mode, the pll is enabled but bypassed. because the pll is bypassed, the processors core clock (cclk) and system clock (sclk) run at the input clock (clkin) frequency. dma access is available to appropri ately configured l1 memories. in the active mode, it is possibl e to disable the pll through the pll control register (pll_ctl). if disabled, the pll must be re-enabled before transitioning to the full-on or sleep modes. table 5. power settings mode/state pll pll bypassed core clock (cclk) system clock (sclk) core power full-on enabled no enabled enabled on active enabled/ disabled yes enabled enabled on sleep enabled disabled enabled on deep sleep disabled disabled disabled on hibernate disabled disabled disabled off
rev. f | page 14 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f sleep operating modehigh dynamic power savings the sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (cclk). the pll and system clock (sclk), however, continue to operate in this mode. typi- cally, an external event or rtc ac tivity wakes up the processor. when in the sleep mode, assert ion of a wake-up event enabled in the sic_iwrx register causes the processor to sense the value of the bypass bit in the pll control register (pll_ctl). if bypass is disabled, the processor transitions to the full on mode. if bypass is enabled, the processor will transition to the active mode. when in the sleep mode, system dma access to l1 memory is not supported. deep sleep operating modemaximum dynamic power savings the deep sleep mode maximizes dynamic power savings by dis- abling the clocks to the processor core (cclk) and to all synchronous peripherals (sclk) . asynchronous peripherals such as the rtc may still be ru nning but will not be able to access internal resources or external memory. this powered- down mode can only be exited by assertion of the reset interrupt (reset ) or by an asynchronous interrupt generated by the rtc. when in deep sleep mode, an rtc asynchronous interrupt causes the processor to transition to the active mode. assertion of reset while in deep sleep mo de causes the proces- sor to transition to the full-on mode. hibernate statemaximum static power savings the hibernate state maximizes stat ic power savings by disabling the voltage and clocks to the processor core (cclk) and to all the synchronous peripherals (sclk). the internal voltage regu- lator for the processor can be shut off by writing b#00 to the freq bits of the vr_ctl register. this sets the internal power supply voltage (v ddint ) to 0 v to provide the lowest static power dissipation. any critical information stored internally (memory contents, register contents, etc.) must be written to a nonvolatile storage device prior to removing power if the processor state is to be preserved. since v ddext can still be supplied in this mode, all of the external pins three-st ate, unless otherwise specified. this allows other devices that may be connected to the proces- sor to still have power applied without drawing unwanted current. the internal supply regu lator can be woken up either by a real-time clock wake-up, by can bus traffic, by asserting the reset pin, or by an extern al source via the gpw pin. power savings as shown in table 6 , the ADSP-BF539/ADSP-BF539f proces- sors support five different power domains. the use of multiple power domains maximizes flexibility, while maintaining com- pliance with industry standards and conventions: ? the 3.3 v v ddrtc power domain supplies the rtc i/o and logic so that the rtc can rema in functional when the rest of the chip is powered off. ? the 3.3 v mxevdd power domain supplies the mxvr crystal and is separate to provide noise isolation. ? the 1.25 v mpivdd power domain supplies the mxvr pll and is separate to provide noise isolation. ? the 1.25 v v ddint power domain supplies all internal logic except for the rtc logic and the mxvr pll. ? the 3.3 v v ddext power domain supplie s all i/o except for the rtc and mxvr crystals. there are no sequencing requir ements for the various power domains. the v ddrtc should either be connected to an isolated supply such as a battery (if the rtc is to operate while the rest of the chip is powered down) or should be connected to the v ddext plane on the board. the v ddrtc should remain powered when the processor is in hibernate st ate and should also remain pow- ered even if the rt c functionality is not being used in an application. the mxevdd should be connected to the v ddext plane on the board at a single lo cation with local bypass capaci- tors. the mxevdd should remain powered when the processor is in hibernate state and should also remain powered even when the mxvr functionality is not being used in an application. the mpivdd shou ld be connected to the v ddint plane on the board at a single location through a ferrite bead with local bypass capacitors. the power dissipated by a processo r is largely a function of the clock frequency of the processor and the square of the operating voltage. for example, reducing the clock frequency by 25% results in a 25% reduction in dynamic power dissipation, while reducing the voltage by 25% reduces dynamic power dissipation by more than 40%. further, thes e power savings are additive in that, if the clock frequency and supply voltage are both reduced, the power savings can be dramatic. the dynamic power management feature of the ADSP-BF539/ADSP-BF539f processo rs allow both the proces- sor input voltage (v ddint ) and clock frequency (f cclk ) to be dynamically controlled. the savings in power dissipation can be modeled using the power savings factor and % p ower savings calculations. the power savings factor is calculated as where: f cclknom is the nominal core clock frequency. f cclkred is the reduced core clock frequency. v ddintnom is the nominal internal supply voltage. table 6. power domains power domain v dd range rtc crystal i/o and logic v ddrtc mxvr crystal i/o mxevdd mxvr pll analog and logic mpivdd all internal logic except rtc and mxvr pll v ddint all i/o except rtc and mxvr crystals v ddext power savings factor f cclkred f cclknom ------------------- - v ddintred v ddintnom ------------------------ ?? ?? 2 ? t red t nom ---------- ? ? ? ? ? =
ADSP-BF539 / ADSP-BF539f rev. f | page 15 of 60 | october 2013 v ddintred is the reduced internal supply voltage. t nom is the duration running at f cclknom . t red is the duration running at f cclkred . the power savings factor is calculated as voltage regulation the blackfin processors provid e an on-chip voltage regulator that can generate appropriate v ddint voltage levels from the v ddext supply. see operating conditions on page 26 for regula- tor tolerances and acceptable v ddext ranges for specific models. ? the regulator controls the intern al logic voltage levels and is programmable with the voltag e regulator control register (vr_ctl) in increments of 50 mv. to reduce standby power consumption, the internal voltag e regulator can be programmed to remove power to the proc essor core while i/o power (v ddrtc , mxevdd, v ddext ) is still supplied. while in the hibernate state, i/o power is still being applied, eliminating the need for external buffers. the voltage re gulator can be activated from this power-down state through an rtc wake-up, a can wake- up, an mxvr wake-up, a general-purpose wake-up, or by asserting reset , all of which will then in itiate a boot sequence. the regulator can also be disabl ed and bypassed at the users discretion. clock signals the ADSP-BF539/ADSP-BF539f proc essors can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. if an external clock is used, it should be a ttl-compatible signal and must not be halted, changed, or operated below the speci- fied frequency during normal operation. this signal is connected to the processors cl kin pin. when an external clock is used, the xtal pin must be left unconnected. alternatively, because the proce ssors include an on-chip oscilla- tor circuit, an external crysta l can be used. for fundamental frequency operation, use the circuit shown in figure 7 . a paral- lel-resonant, fundamental freq uency, microprocessor-grade crystal is connected across the clkin and xtal pins. the on- chip resistance between clkin and the xtal pin is in the 500 kw range. further parallel re sistors are typically not recom- mended. the two capacitors and the series resistor, shown in figure 7 , fine tune the phase and amplitude of the sine fre- quency. the capacitor and re sistor values, shown in figure 7 , are typical values only. the capa citor values are dependent upon the crystal manufacturers load capacitance recommendations and the physical pcb layout. the resistor value depends on the drive level specified by the crys tal manufacturer. system designs should verify the cust omized values based on careful investiga- tion on multiple devices over the allowed temperature range. a third-overtone crystal can be used at frequencies above 25 mhz. the circuit is then modifi ed to ensure crystal operation only at the third overtone, by adding a tuned inductor circuit as shown in figure 7 . as shown in figure 8 on page 16 , the core clock (cclk) and system peripheral clock (sclk) are derived from the input clock (clkin) signal. an on-chip pll is capable of multiplying the clkin signal by a user prog rammable 0.5 to 64 multipli- cation factor (bounded by specified minimum and maximum vco frequencies). the default multiplier is 10, but it can be modified by a software instru ction sequence. on-the-fly fre- quency changes can be effected by simply writing to the pll_div register. ? see switching regulator design consider ations for adsp-bf533 blackfin processors (ee-228) . figure 6. voltage regulator circuit % power savings 1 power savings factor ? ?? 100% ? = v ddext (low-inductance) v ddint vr out 100f vr out gnd short and low- inductance wire v ddext + + + 100f 100f 10f low esr 100nf set of decoupling capacitors fds9431a zhcs1000 note: designer should minimize trace length to fds9431a. 10h figure 7. external crystal connections clkin clkout xtal en 18pf* 18pf* for overtone operation only v ddext to pll circuitry note: values marked with * must be customized depending on the crystal and layout. please analyze carefully. blackfin 700 : 0 : * 1m :
rev. f | page 16 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f all on-chip peripherals are clocked by the system clock (sclk). the system clock frequency is programmable by means of the ssel3C0 bits of the pll_div re gister. the values programmed into the ssel fields define a divide ratio between the pll output (vco) and the system clock. sclk divider values are 1 through 15. table 7 illustrates typical system clock ratios. the maximum frequency of the system clock is f sclk . note that the divisor ratio must be chosen to limit the system clock fre- quency to its maximum of f sclk . the ssel value can be changed dynamically without any pll lock latencies by writing the appropriate values to the p ll divisor register (pll_div). note that when the ssel value is changed, it will affect all the peripherals that derive their cloc k signals from the sclk signal. the core clock (cclk) freque ncy can also be dynamically changed by means of the csel1C0 bits of the pll_div register. supported cclk divider ratios are 1, 2, 4, and 8, as shown in table 8 . this programmable core cloc k capability is useful for fast core frequency modifications. booting modes the ADSP-BF539/ADSP-BF539f pr ocessors have three mecha- nisms (listed in table 9 ) for automatically loading internal l1 instruction memory after a reset. a fourth mode is provided to execute from external memory, bypassing the boot sequence. the bmode pins of the reset configuration register, sampled during power-on resets and soft ware initiated resets, implement the following modes: ? execute from 16-bit external memory C execution starts from address 0x2000 0000 with 16-bit packing. the boot rom is bypassed in this mode. all configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle r/w access times; 4-cycle setup). ? boot from 8-bit or 16-bit exte rnal flash memory C the 8-bit flash boot routine located in boot rom memory space is set up using asynchronous memory bank 0. for ADSP-BF539f processors, if fce is connected to ams0 , then the on-chip flash is booted. all configuration settings are set for the slowest device possible (3-cycle hold time; 15-cycle r/w access times; 4-cycle setup). ? boot from spi serial eeprom/flash (8-, 16-, or 24-bit addressable, or atmel at45db041, at45db081, or at45db161) connected to spi0 C the spi0 port uses the pf2 output pin to select a single spi eeprom/flash device, submits a read command an d successive address bytes (0x00) until a valid 8-, 16-, or 24-bit, or atmel addressable device is detected, and begins clocking data into the begin- ning of the l1 instruction memory. ? boot from spi host device co nnected to spi0 C the black- fin processor operates in spi slave mode and is configured to receive the bytes of the .ldr file from an spi host (mas- ter) agent. to hold off the ho st device from transmitting while the boot rom is busy, th e blackfin processor asserts a gpio pin, called host wait (hwait), to signal the host device not to send any more bytes until the flag is deas- serted. the flag is chosen by the user and this information is transferred to the blackfin processor via bits 10:5 of the flag header in the .ldr image. for each of the boot modes, a 10-byte header is first read from an external memory device. the header specifies the number of bytes to be transferred and th e memory destination address. figure 8. frequency mo dification methods table 7. example system clock ratios signal name ssel3C0 divider ratio vco/sclk example frequency ratios (mhz) vco sclk 0001 1:1 100 100 0110 6:1 300 50 1010 10:1 500 50 table 8. core clock ratios signal name csel1C0 divider ratio vco/cclk example frequency ratios vco cclk 00 1:1 300 300 01 2:1 300 150 10 4:1 500 125 11 8:1 200 25 pll 0.5 u to 64 u 1:15 1,2,4,8 vco sclk d cclk sclk d 133mhz clkin fine adjustment requires pll sequencing coarse adjustment on-the-fly cclk sclk table 9. booting modes bmode1C0 description 00 execute from 16-bit external memory (bypass boot rom) 01 boot from 8-bit or 16-bit flash or boot from on-chip flash (ADSP-BF539f only) 10 boot from spi serial master connected to spi0 11 boot from spi serial slave eeprom/flash (8-,16-, or 24-bit address range, or atmel at45db041, at45db081, or at45db161serial flash) connected to spi0
ADSP-BF539 / ADSP-BF539f rev. f | page 17 of 60 | october 2013 multiple memory blocks can be loaded by any boot sequence. once all blocks are loaded, pr ogram execution commences from the start of l1 instruction sram. in addition, bit 4 of the reset configuration register can be set by application code to bypass the normal boot sequence during a software reset. for this case, th e processor jumps directly to the beginning of l1 instruction memory. to augment the boot modes, a se condary software loader is pro- vided that adds additional booting mechanisms. this secondary loader provides the ability to boot from 16-bit flash memory, fast flash, variable baud rate, and other sources. in all boot modes except bypass, program exec ution starts from on-chip l1 memory address 0xffa0 0000. instruction set description the blackfin processor family a ssembly language instruction set employs an algebraic syntax desi gned for ease of coding and readability. the instructions have been specifically tuned to pro- vide a flexible, densely encoded instruction set that compiles to a very small final memory size. th e instruction set also provides fully featured multifunction instructions that allow the pro- grammer to use many of the proce ssor core resources in a single instruction. coupled with many features more often seen on microcontrollers, this instruction set is very efficient when com- piling c and c++ source code. in addition, the architecture supports both user (algorithm/app lication code) and supervisor (o/s kernel, device drivers, debuggers, isrs) modes of opera- tion, allowing multiple levels of access to core processor resources. the assembly language, which takes advantage of the proces- sors unique architecture, offe rs the following advantages: ? seamlessly integrated dsp/cpu features are optimized for both 8-bit and 16-bit operations. ? a multi-issue load/store modified harvard architecture, which supports two 16-bit mac or four 8-bit alu plus two load/store plus two pointer updates per cycle. ? all registers, i/o, and memory are mapped into a unified 4g byte memory space, prov iding a simplified program- ming model. ? microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and ex traction; integer operations on 8-, 16-, and 32-bit data ty pes; and separate user and supervisor stack pointers. ? code density enhancements, wh ich include intermixing of 16-bit and 32-bit instructions (n o mode switching, no code segregation). frequently used instructions are encoded in 16 bits. development tools analog devices supports its proce ssors with a complete line of software and hardware development tools, including integrated development enviro nments (which include crosscore ? embed- ded studio and/or visualdsp++ ? ), evaluation products, emulators, and a wide vari ety of software add-ins. integrated development environments (ides) for c/c++ software writing and editing, code generation, and debug support, analog devices offers two ides. the newest ide, crosscore embe dded studio, is based on the eclipse tm framework. supporting most analog devices proces- sor families, it is the ide of choice for future processors, including multicore devices. crosscore embedded studio seamlessly integrates available so ftware add-ins to support real time operating systems, file systems, tcp/ip stacks, usb stacks, algorithmic software modules, and evaluation hardware board support packages. for more information visit www.analog.com/cces . the other analog devices ide, visualdsp++, supports proces- sor families introduced prior to the release of crosscore embedded studio. this ide incl udes the analog devices vdk real time operating system and an open source tcp/ip stack. for more information visit www.analog.com/visualdsp . note that visualdsp++ will not suppo rt future analog devices processors. ez-kit lite evaluation board for processor evaluation, analog devices provides wide range of ez-kit lite ? evaluation boards. incl uding the processor and key peripherals, the evaluation board also supports on-chip emulation capabilities and other evaluation and development features. also available are various ez-extenders ? , which are daughter cards delivering additional specialized functionality, including audio and video processing. for more information visit www.analog.com and search on ezkit or ezextender. ez-kit lite evaluation kits for a cost-effective way to lear n more about developing with analog devices processors, analog devices offer a range of ez- kit lite evaluation kits. each evaluation kit includes an ez-kit lite evaluation board, directions for downloading an evaluation version of the available ide(s), a usb cable, and a power supply. the usb controller on the ez-kit lite board connects to the usb port of the users pc, enab ling the chosen ide evaluation suite to emulate the on-board pr ocessor in-circuit. this permits the customer to download, execut e, and debug programs for the ez-kit lite system. it also su pports in-circuit programming of the on-board flash device to store user-specific boot code, enabling standalone operation. with the full version of cross- core embedded studio or visualdsp++ installed (sold separately), engineers can deve lop software for supported ez- kits or any custom system util izing supported analog devices processors. software add-ins for crosscore embedded studio analog devices offers software add-ins which seamlessly inte- grate with crosscore embedded stud io to extend its capabilities and reduce development time. add-ins include board support packages for evaluation hardwa re, various middleware pack- ages, and algorithmic modules. documentation, help, configuration dialogs, and coding examples present in these add-ins are viewable through th e crosscore embedded studio ide once the add-in is installed.
rev. f | page 18 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f board support packages for evaluation hardware software support for the ez-kit lite evaluation boards and ez- extender daughter cards is prov ided by software add-ins called board support packages (bsps). the bsps contain the required drivers, pertinent release notes, and select example code for the given evaluation hardware. a downlo ad link for a specific bsp is located on the web page for the associated ez-kit or ez- extender product. the link is found in the product download area of the product web page. middleware packages analog devices separately offers middleware add-ins such as real time operating systems, file systems, usb stacks, and tcp/ip stacks. for more information see the following web pages: ? www.analog.com/ucos3 ? www.analog.com/ucfs ? www.analog.com/ucusbd ? www.analog.com/lwip algorithmic modules to speed development, analog de vices offers add-ins that per- form popular audio and video processing algorithms. these are available for use with both cr osscore embedded studio and visualdsp++. for more information visit www.analog.com and search on blackfin software modules or sharc software modules. designing an emulator-compatible dsp board (target) for embedded system test and de bug, analog devices provides a family of emulators. on each jtag dsp, analog devices sup- plies an ieee 1149.1 jtag test access port (tap). in-circuit emulation is facilitated by use of this jtag interface. the emu- lator accesses the processors internal features via the processors tap, allowing the de veloper to load code, set break- points, and view variables, memory, and registers. the processor must be halted to se nd data and commands, but once an operation is completed by the emulator, the dsp system is set to run at full speed with no im pact on system timing. the emu- lators require the target board to include a header that supports connection of the dsps jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor connections, signal buffering, signal ter- mination, and emulator pod logic, see the engineer-to-engineer note analog devices jtag emulation technical reference (ee-68) on the analog devices website ( www.analog.com )use site search on ee-68. this document is updated regularly to keep pace with improvemen ts to emulator support. example connections and layout considerations figure 9 shows an example circuit connection of the ADSP-BF539/ADSP-BF539f to a mo st network. this diagram is intended as an example, and exact connections and recom- mended circuit values should be obtained from analog devices. mxvr board layout guidelines mlf pin ?capacitors: c1: 0.1 ? f (pps type, 2% tolerance recommended) c2: 0.01 ? f (pps type, 2% tolerance recommended) ?resistor: r1: 220 ? (1% tolerance) ? the rc network connected to the mlf pin should be located physically close to the mlf pin on the board. ? the rc network should be wired up and connected to the mlf pin using wide traces. ? the capacitors in the rc ne twork should be grounded to mxegnd. ? the rc network should be shielded using mxegnd traces. ? avoid routing other switching signals near the rc network to avoid crosstalk. mxi driven with external cloc k oscillator ic (recommended) ? mxi should be driven with the clock output of a 49.152 mhz or 45.1584 mhz clock oscillator ic. ? mxo should be left unconnected. ? avoid routing other switching signals near the oscillator and clock output trace to avoid crosstalk. when not possi- ble, shield traces with ground. mxi/mxo with ex ternal crystal ? the crystal must be a 49.152 mhz or 45.1584 mhz funda- mental mode crystal. ? the crystal and load capacitors should be placed physically close to the mxi and mxo pins on the board. ? the load capacitors should be grounded to mxegnd. ? the crystal and load capacito rs should be wired up using wide traces. ? board trace capacitance on ea ch lead should not be more than 3 pf. ? trace capacitance plus load capacitance should equal the load capacitance specification for the crystal. ? avoid routing other switching signals near the crystal and components to avoid crosstalk. when not possible, shield traces and components with ground. mxegndCmxvr crystal oscilla tor and mxvr pll ground ? should be routed with wide traces or as ground plane. ? should be tied together to ot her board grounds at only one point on the board. ? avoid routing other switching signals near to mxegnd to avoid crosstalk.
ADSP-BF539 / ADSP-BF539f rev. f | page 19 of 60 | october 2013 mxevddCmxvr crystal oscillator 3.3 v power ? should be routed with wide traces or as power plane. ? locally bypass mxevdd with 0.1 ?? f and 0.01 ? f decou- pling capacitors to mxegnd. ? avoid routing other switching signals near to mxevdd to avoid crosstalk. mpivddCmxvr pll 1.25 v power ? should be routed with wide traces or as power plane. ? a ferrite bead should be placed between the 1.25 v v ddint power plane and the mpivdd pin for noise isolation. ? locally bypass mpivdd with 0.1 ? f and 0.01 ? f decou- pling capacitors to mxegnd. ? avoid routing other switching signals near to mpivdd to avoid crosstalk. fiber optic transceiver (fot) connections ? the traces between the ADSP-BF539/ADSP-BF539f pro- cessor and the fot should be kept as short as possible. ? the receive data trace conne cting the fot receive data output pin to the adsp-b f539/ADSP-BF539f mrx input pin should not have a series termination resistor. the edge rate of the fot receive data signal driven by the fot is typically very slow, and further degradation of the edge rate is not desirable. ? the transmit data trace co nnecting the processors mtx output pin to the fot transmit data input pin should have a 27 w series termination resistor placed close to the ADSP-BF539/ADSP-BF539f mtx pin. ? the receive data trace and the transmit data trace between the processor and the fot shou ld not be routed close to each other in paralle l over long distances to avoid crosstalk. voltage regulator layout guidelines regulator external component placement, board routing, and bypass capacitors all have a significant effect on noise injected into the other analog circuits on-chip. the vrout1-0 traces and voltage regulator external components should be consid- ered as noise sources when doin g board layout and should not be routed or placed near sensitive circuits or components on the board. all internal and i/o power supplies should be well bypassed with bypass capacitors placed as close to the ADSP-BF539/ADSP-BF539f as possible. for further details on the on-chi p voltage regulator and related board design guidelines, see the switching regulator design considerations for adsp-bf533 blackfin processors (ee-228) applications note on the analog devices website ( www.analog.com )use site search on ee-228. figure 9. example connectio ns of ADSP-BF539/ADSP-BF539f to most network fb clko mxegnd most network audio channels mxegnd mpivdd power gating circuit most fot rx_vdd tx_vdd tx_data rx_data status audio dac 27 : r1 220 : c1 0.1 p f 0.1 p f 0.01 p f c2 0.01 p f f 49.152mhz oscillator ADSP-BF539f mxi mxo mlf mtxon mtx mrx mrxon mmclk mfs mbclk tsclk0 rsclk0 rfs0 dt0pri sdata l/rclk bclk mclk 33 : 33 : 33 : vddint (1.25v) 5 v 5 v b
rev. f | page 20 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f additional information the following publications th at describe the ADSP-BF539/ ADSP-BF539f processors (and related processors) can be ordered from any analog devices sales office or accessed elec- tronically on our website: ? getting started with blackfin processors ? ADSP-BF539 blackfin proc essor hardware reference ? adsp-bf53x/adsp-bf56x blackfin processor program- ming reference ? ADSP-BF539 blackfin processor anomaly list related signal chains a signal chain is a series of signal-conditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stor ed data) in tandem, with the output of one portion of the ch ain supplying input to the next. signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. for more information about this term and related topics, see the "signal chain" entry in wikipedia or the glossary of ee terms on the analog devices website. analog devices eases signal proc essing system development by providing signal proc essing components that are designed to work together well. a tool for viewing relationships between specific applications and related components is available on the www.analog.com website. the application signal chains pa ge in the circuits from the lab tm site ( http://www.analog. com/signalchains ) provides: ? graphical circuit block diag ram presentation of signal chains for a variety of circuit types and applications ? drill down links for components in each chain to selection guides and application information ? reference designs applying best practice design techniques
ADSP-BF539 / ADSP-BF539f rev. f | page 21 of 60 | october 2013 pin descriptions ADSP-BF539/ADSP-BF539f processo r pin definitions are listed in table 10 . all pins are three-stated during and immediately after reset, except the memory interface, asynchronous memory control, and synchronous memory control pins. these pins are all driven high, with the exception of clkout, which toggles at the system clock rate. if br is active (whether or not reset is asserted), the memory pins are al so three-stated. all unused i/o pins have their input buffers disabled with the exception of the pins that need pull-ups or pull- downs, as noted in the table. during hibernate, all outputs are three-stated unless otherwise noted in table 10 . in order to maintain maximum functionality and reduce pack- age size and pin count, some pins have dual, multiplexed functionality. in cases where pin functionality is reconfigurable, the default state is shown in plain text, while alternate function- ality is shown in italics. table 10. pin descriptions pin name type description driver type 1 memory interface addr19C1 o address bus for async/sync access a data15C0 i/o data bus for async/sync access a abe1C0 /sdqm1C0 o byte enables/data masks for async/sync access a br i bus request (this pin should be pulled high when not used.) bg obus grant a bgh o bus grant hang a asynchronous memory control ams3C0 o bank select a ardy i hardware ready control (this pin should always be pulled low when not used.) aoe o output enable a are oread enable a awe owrite enable a flash control fce i flash enable (this pin is internally connected to gnd on the ADSP-BF539.) freset i flash reset (this pin is internally connected to gnd on the ADSP-BF539.) synchronous memory control sras o row address strobe a scas o column address strobe a swe owrite enable a scke o clock enable (this pin must be pulled low through a 10 k ? resistor if hibernate state is used and sdram contents need to be preserved during hibernate.) a clkout o clock output b sa10 o a10 pin a sms o bank select a timers tmr0 i/o timer 0 c tmr1/ ppi_fs1 i/o timer 1/ ppi frame sync1 c tmr2/ ppi_fs2 i/o timer 2/ ppi frame sync2 c
rev. f | page 22 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f parallel peripheral interface port/gpio pf0/ spi0ss i/o programmable flag 0/ spi0 slave select input c pf1 /spi0sel1 /taclk i/o programmable flag 1/ spi0 slave select enable 1/timer alternate clock c pf2/ spi0sel2 i/o programmable flag 2/ spi0 slave select enable 2 c pf3/ spi0sel3 /ppi_fs3 i/o programmable flag 3/ spi0 slave select enable 3/ppi frame sync 3 c pf4/ spi0sel4 /ppi15 i/o programmable flag 4/ spi0 slave select enable 4/ppi 15 c pf5/ spi0sel5 /ppi14 i/o programmable flag 5/ spi0 slave select enable 5/ppi 14 c pf6/ spi0sel6 /ppi13 i/o programmable flag 6/ spi0 slave select enable 6/ppi 13 c pf7/ spi0sel7 /ppi12 i/o programmable flag 7/ spi0 slave select enable 7/ppi 12 c pf8/ ppi11 i/o programmable flag 8/ ppi 11 c pf9/ ppi10 i/o programmable flag 9/ ppi 10 c pf10/ ppi9 i/o programmable flag 10/ ppi 9 c pf11/ ppi8 i/o programmable flag 11/ ppi 8 c pf12/ ppi7 i/o programmable flag 12/ ppi 7 c pf13/ ppi6 i/o programmable flag 13/ ppi 6 c pf14/ ppi5 i/o programmable flag 14/ ppi 5 c pf15/ ppi4 i/o programmable flag 15/ ppi 4 c ppi3C0 i/o ppi3C0 c ppi_clk/ tmrclk i ppi clock/ external time r reference controller area network cantx/ pc0 i/o 5 v can transmit/ gpio c canrx/ pc1 i/od 5 v can receive/ gpio c 2 media transceiver (mxvr) /general-purpose i/o mtx/ pc5 i/o mxvr transmit data/ gpio c mtxon / pc9 i/o mxvr transmit fot on/ gpio c mrx/ pc4 i/od 5 v mxvr receive data/ gpio (this pin should be pulled low when not used.) c 2 mrxon i 5 v mxvr fot receive on (this pin should be pulled high when not used.) c mxi i mxvr crystal input (this pin should be pulled low when not used.) mxo o mxvr crystal output (this pin should be left unconnected when not used.) mlf a i/o mxvr loop filter (this pin should be pulled low when not used.) mmclk/ pc6 i/o mxvr master clock/ gpio c mbclk/ pc7 i/o mxvr bit clock/ gpio c mfs/ pc8 i/o mxvr frame sync/ gpio c gp i gpio pc4C9 enable (this pin should be pulled low when mxvr is used.) 2-wire interface port s these pins are open-drain and require a pull-up resistor. see version 2.1 of the i 2 c specification for proper resistor values. sda0 i/o 5 v twi0 serial data e scl0 i/o 5 v twi0 serial clock e sda1 i/o 5 v twi1 serial data e scl1 i/o 5 v twi1 serial clock e table 10. pin descriptions (continued) pin name type description driver type 1
ADSP-BF539 / ADSP-BF539f rev. f | page 23 of 60 | october 2013 serial port0 rsclk0 i/o sport0 receive serial clock d rfs0 i/o sport0 receive frame sync c dr0pri i sport0 receive data primary dr0sec i sport0 receive data secondary tsclk0 i/o sport0 transmit serial clock d tfs0 i/o sport0 transmit frame sync c dt0pri o sport0 transmit data primary c dt0sec o sport0 transmit data secondary c serial port1 rsclk1 i/o sport1 receive serial clock d rfs1 i/o sport1 receive frame sync c dr1pri i sport1 receive data primary dr1sec i sport1 receive data secondary tsclk1 i/o sport1 transmit serial clock d tfs1 i/o sport1 transmit frame sync c dt1pri o sport1 transmit data primary c dt1sec o sport1 transmit data secondary c serial port2 rsclk2/ pe0 i/o sport2 receive serial clock/ gpio d rfs2/ pe1 i/o sport2 receive frame sync/ gpio c dr2pri/ pe2 i/o sport2 receive data primary/ gpio c dr2sec/ pe3 i/o sport2 receive data secondary/ gpio c tsclk2/ pe4 i/o sport2 transmit serial clock/ gpio d tfs2/ pe5 i/o sport2 transmit frame sync/ gpio c dt2pri / pe6 i/o sport2 transmit data primary/ gpio c dt2sec/ pe7 i/o sport2 transmit data secondary/ gpio c serial port3 rsclk3/ pe8 i/o sport3 receive serial clock/ gpio d rfs3/ pe9 i/o sport3 receive frame sync/ gpio c dr3pri/ pe10 i/o sport3 receive data primary/ gpio c dr3sec/ pe11 i/o sport3 receive data secondary/ gpio c tsclk3/ pe12 i/o sport3 transmit serial clock/ gpio d tfs3/ pe13 i/o sport3 transmit frame sync/ gpio c dt3pri / pe14 i/o sport3 transmit data primary/ gpio c dt3sec/ pe15 i/o sport3 transmit data secondary/ gpio c table 10. pin descriptions (continued) pin name type description driver type 1
rev. f | page 24 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f spi0 port mosi0 i/o spi0 master out slave in c miso0 i/o spi0 master in slave out (this pin sh ould always be pulled high through a 4.7 k ? resistor if booting via the spi port.) c sck0 i/o spi0 clock d spi1 port mosi1/ pd0 i/o spi1 master out slave in/ gpio c miso1/ pd1 i/o spi1 master in slave out/ gpio c sck1/ pd2 i/o spi1 clock/ gpio d spi1ss / pd3 i/o spi1 slave select input/ gpio d spi1sel1 / pd4 i/o spi1 slave select enable/ gpio d spi2 port mosi2 / pd5 i/o spi2 master out slave in/ gpio c miso2/ pd6 i/o spi2 master in slave out/ gpio c sck2/ pd7 i/o spi2 clock/ gpio d spi2ss / pd8 i/o spi2 slave select input/ gpio d spi2sel1 / pd9 i/o spi2 slave select enable/ gpio d uart0 port rx0 i uart receive tx0 o uart transmit c uart1 port rx1/ pd10 i/o uart1 receive/ gpio d tx1/ pd11 i/o uart1 transmit/ gpio d uart2 port rx2 / pd12 i/o uart2 receive/ gpio d tx2/ pd13 i/o uart2 transmit/ gpio d real-time clock rtxi i rtc crystal input (this pin should be pulled low when not used.) rtxo o rtc crystal output (does not three-state in hibernate.) jtag port tck i jtag clock tdo o jtag serial data out c tdi i jtag serial data in tms i jtag mode select trst i jtag reset (this pin should be pulled low if the jtag port will not be used.) emu o emulation output c clock clkin i clock/crystal input xtal o crystal output table 10. pin descriptions (continued) pin name type description driver type 1
ADSP-BF539 / ADSP-BF539f rev. f | page 25 of 60 | october 2013 mode controls reset i reset nmi i nonmaskable interrupt (this pin shou ld be pulled high when not used.) bmode1C0 i boot mode strap (these pins must be pulled to the state required for the desired boot mode.) voltage regulator vrout1C0 o external fet drive 0 (these pins should be left unconnected when not used.) supplies v ddext pi/o power supply v ddint p internal power supply v ddrtc p real-time clock power supply (this pin should be connected to v ddext when not used and should remain powered at all times.) mpivdd p mxvr internal power supply mxevdd p mxvr external power supply mxegnd g mxvr ground gnd g ground 1 refer to figure 34 on page 50 to figure 43 on page 51 . 2 this pin is 5 v-tolerant when configured as an input and an open-drain when configure d as an output; therefore, only the vol cu rves in figure 38 on page 50 and figure 39 on page 51 and the fall time curves in figure 51 on page 53 and figure 52 on page 53 apply when configured as an output. table 10. pin descriptions (continued) pin name type description driver type 1
rev. f | page 26 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f specifications component specifications are subject to change without notice. operating conditions the following tables describe the voltage/frequency require- ments for the adsp-bf538/adsp -bf538f processor clocks. take care in selecting msel, ssel, and csel ratios so as not to exceed the maximum core clock ( table 11 ) and system clock ( table 13 ) specifications. table 12 describes phase-locked loop operating conditions. parameter conditions min nom max unit v ddint internal supply voltage 1, 2 1 parameter value applies also to mpivdd. 2 the regulator can generate v ddint at levels of 1.0 v to 1.2 v with C5% to +10% tolerance and 1.25 v with C4% to +10% tolerance. 0.95 1.25 1.375 v v ddext external supply voltage 3 3 parameter value applies also to mxevdd. 2.7 3.3 3.6 v v ddrtc real-time clock power supply voltage 2.7 3.3 3.6 v v ih high level input voltage 4 4 the 3.3 v tolerant pins are capable of accepting up to 3.6 v maximum v ih the following bidirectional pins are 3.3 v to lerant: data15C0, sck2 C0, miso2C0, mosi2C0, pf15C0, ppi3C0, mtxon , mmclk, mbclk, mfs, mtx, spi1ss , spi1sel1 , spi2ss , spi2sel1 , rx2C1, tx2C1, dt2pri, dt2sec, tsclk3C0, dr2pri, dr2sec, dt3pri, dt3sec, rsclk3C0, tfs3C0, rfs3C0, dr3pri, dr3sec, and tmr2C0. the following input-only pins are 3.3 v tolerant: reset , rx0, tck, tdi, tms, trst , ardy, bmode1C0, br , dr0pri, dr0sec, dr1pri, dr1sec, nmi , ppi_clk, rtxi, and gp. v ddext = maximum 2.0 v v ih5v high level input voltage 5 5 the 5 v tolerant pins are capable of accepting up to 5.5 v maximum v ih . the following bidirectional pins are 5 v tole rant: scl0, scl1, sda0, sda1, and cantx. the following input-only pins are 5 v tolerant: canrx, mrx, mrxon . v ddext = maximum 2.0 v v ihclkin high level input voltage 6 6 parameter value applies to the clkin and mxi input pins. v ddext = maximum 2.2 v v il low level input voltage 4, 7 7 parameter value applies to a ll input and bidirectional pins. v ddext = minimum +0.6 v v il5v low level input voltage 5 v ddext = minimum +0.8 v t j junction temperature 316-ball chip scale ball grid array package (csp_bga) 533 mhz @ t ambient = C40c to +85c C40 +110 c table 11. core clock (cclk) requirements parameter internal regulator setting max unit f cclk clk frequency (v ddint = 1.2 v minimum) 1.25 v 533 mhz f cclk clk frequency (v ddint = 1.14 v minimum) 1.20 v 500 mhz f cclk clk frequency (v ddint = 1.045 v minimum) 1.10 v 444 mhz f cclk clk frequency (v ddint = 0.95 v minimum) 1.00 v 400 mhz table 12. phase-locked loop operating conditions parameter min max unit f vco voltage controlled oscillator (vco) frequency 50 max f cclk mhz table 13. system clock (sclk) requirements parameter 1 max unit f sclk clkout/sclk frequency (v ddint ? 1.14 v) 133 2 mhz f sclk clkout/sclk frequency (v ddint ? 1.14 v) 100 mhz 1 t sclk (= 1/f sclk ) must be greater than or equal to t cclk 2 guaranteed to t sclk = 7.5 ns. see table 26 on page 36 .
ADSP-BF539 / ADSP-BF539f rev. f | page 27 of 60 | october 2013 electrical characteristics parameter 1 1 specifications subject to change without notice. test conditions min typ max unit v oh high level output voltage 2 2 applies to output an d bidirectional pins. v ddext = +3.0 v, i oh = C0.5 ma 2.4 v v ol low level output voltage 2 v ddext = 3.0 v, i ol = 2.0 ma 0.4 v i ih high level input current 3 3 applies to input pins except jtag inputs. v ddext = maximum, v in = v dd maximum 10.0 a i ihp high level input current jtag 4 4 applies to jtag input pins (tck, tdi, tms, trst ). v ddext = maximum, v in = v dd maximum 50.0 a i il low level input current 3 v ddext = maximum, v in = 0 v 10.0 a i ozh three-state leakage current 5 5 applies to three-statable pins. v ddext = maximum, v in = v dd maximum 10.0 a i ozl three-state leakage current 5 v ddext = maximum, v in = 0 v 10.0 a c in input capacitance 6, 7 6 applies to all signal pins. 7 guaranteed, but not tested. f cclk = 1 mhz, t ambient = 25c, v in = 2.5 v 4 8 pf i dddeepsleep 8 8 see the ADSP-BF539 blackfin processo r hardware reference manual for definitions of sleep, deep sl eep, and hibernate operating modes. v ddint current in deep sleep mode v ddint = 1.0 v, f cclk = 0 mhz, t j = 25c, asf = 0.00 7.5 ma i ddsleep v ddint current in sleep mode v ddint = 0.8 v, t j = 25c, sclk = 25 mhz 10 ma i dd - typ v ddint current v ddint = 1.14 v, f cclk = 400 mhz, t j = 25c 130 ma i dd - typ v ddint current v ddint = 1.2 v, f cclk = 500 mhz, t j = 25c 168 ma i dd - typ v ddint current v ddint = 1.2 v, f cclk = 533 mhz, t j = 25c 180 ma i ddhibernate 8 v ddext current in hibernate state v ddext = 3.6 v, clkin = 0 mhz, t j = maximum, voltage regulator off (v ddint = 0 v) 50 100 ? a i ddrtc v ddrtc current v ddrtc = 3.3 v, t j = 25c 20 ? a i dddeepsleep 8 v ddint current in deep sleep mode f cclk = 0 mhz 6 table 14 ma i ddint 9 9 see table 15 for the list of i ddint power vectors covered by various activity scaling factors (asf). v ddint current f cclk > 0 mhz i dddeepsleep + ( table 16 asf) ma
rev. f | page 28 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f system designers should refer to estimating power for the adsp-bf538/bf539 blackfin processors (ee-298) , which pro- vides detailed information for optimizing designs for lowest power. all topics discussed in this section are described in detail in ee-298. total power dissi pation has two components: 1. static, including leakage current 2. dynamic, due to transistor switchin g characteristics many operating conditions can also affect po wer dissipation, including temperature, voltage, operating frequency, and pro- cessor activity. electrical characteristics on page 27 shows the current dissipation for internal circuitry (v ddint ). i dddeepsleep speci- fies static power dissipation as a function of voltage (v ddint ) and temperature (see table 14 ), and i ddint specifies the total power specification for the listed te st conditions, including the dynamic component as a function of voltage (v ddint ) and fre- quency ( table 16 ). the dynamic component is also su bject to an activity scaling factor (asf) which represents ap plication code running on the processor ( table 15 ). table 14. static current (ma) 1 v ddint (v) t j (c) 0.80 v 0.85 v 0.90 v 0.95 v 1.00 v 1.05 v 1.10 v 1.15 v 1.20 v 1.25 v 1.30 v 1.32 v 1.375 v C40 6.4 7.7 8.8 10.4 12.0 14.0 16.1 18.9 21.9 25.2 28.7 30.6 35.9 C25 9.2 10.9 12.5 14.5 16.7 19.3 22.1 25.6 29.5 33.7 38.1 40.5 47.2 0 16.818.921.524.427.731.735.840.545.851.658.261.069.8 25 32.9 37.2 41.4 46.2 51.8 57.4 64.2 72.3 80.0 89.3 98.9 103.3 116.4 40 48.4 54.8 60.5 67.1 74.7 82.9 91.6 101.5 112.4 123.2 136.2 142.0 158.7 55 71.2 78.6 86.5 95.8 104.9 115.7 127.1 139.8 153.6 168.0 183.7 191.0 211.8 70 102.3 112.2 122.1 133.5 146.1 159.2 173.9 189.8 206.7 225.5 245.6 254.1 279.6 85 140.7 153.0 167.0 182.5 198.0 216.0 234.3 254.0 276.0 299.1 324.3 334.8 366.6 100 190.6 207.1 224.6 244.0 265.6 285.7 309.0 333.7 360.0 387.8 417.3 431.1 469.3 105 210.2 228.1 245.1 265.6 285.8 309.2 334.0 360.1 385.6 417.2 448.0 461.5 501.1 1 values are guaranteed maximum i dddeepsleep specifications. table 15. activity scaling factors i ddint power vector 1 activity scaling factor (asf) 2 i dd-peak-mxvr 1.36 i dd-high-mxvr 1.32 i dd-peak 1.30 i dd-high 1.28 i dd-typ-mxvr 1.07 i dd-typ 1.00 i dd-app-mxvr 0.92 i dd-app 0.88 i dd-nop-mxvr 0.76 i dd-nop 0.74 i dd-idle-mxvr 0.50 i dd-idle 0.48 1 see ee-298 for power vector definitions. 2 all asf values determined using a 10:1 cclk:sclk ratio.
ADSP-BF539 / ADSP-BF539f rev. f | page 29 of 60 | october 2013 table 16. dynamic current (ma, with asf = 1.0) 1 frequency (mhz) v ddint 0.95 v 1.00 v 1.05 v 1.10 v 1.15 v 1.20 v 1.25 v 1.30 v 1.32 v 1.375 v 50 17.5 19.1 20.5 22.0 23.5 25.4 27.1 29.1 29.7 31.6 100 30.1 32.3 34.4 37.0 39.2 41.7 44.3 46.4 47.6 50.3 200 54.8 58.4 61.8 65.6 69.7 74.3 76.2 82.2 83.4 87.8 250 66.8 71.2 75.7 79.9 84.5 89.8 94.2 99.4 101.2 106.5 300 79.3 84.5 89.0 94.7 100.0 105.5 111.6 116.8 119.3 125.5 375 97.9 103.9 109.9 116.5 122.2 129.7 136.0 142.9 145.9 153.6 400 103.8 110.3 116.9 123.7 130.0 137.5 144.2 151.2 154.5 162.4 425 n/a 116.6 123.7 130.9 137.2 144.7 152.7 159.9 163.3 171.8 475 n/a n/a n/a 145.0 151.8 161.4 169.4 177.8 181.1 190.4 500 n/a n/a n/a n/a 159.9 168.9 177.8 186.3 190.0 199.6 533 n/a n/a n/a n/a n/a 179.8 188.9 198.8 202.2 212.5 1 the values are not guaranteed as standalone maximum specifications, they must be combin ed with static current per the equations of electrical characteristics on page 27 .
rev. f | page 30 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f absolute maximum ratings stresses greater than those listed in table 17 may cause perma- nent damage to the device. these are stress ratings only. functional operation of the device at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd sensitivity package information the information presented in figure 10 and table 19 provides information about how to read the package brand and relate it to specific product features. for a complete listing of product offerings, see the ordering guide on page 60 . table 17. absolute maximum ratings parameter rating internal (core) supply voltage (v ddint ) 1 1 parameter value applies also to mpivdd. C0.3 v to +1.4 v external (i/o) supply voltage (v ddext ) 2 2 parameter value applies also to mxevdd and v ddrtc . C0.3 v to +3.8 v input voltage 3, 4 3 applies to 100% transient duty cycle. for other duty cycles, see table 18 . 4 applies only when v ddext is within specifications. when v ddext is outside speci- fications, the range is v ddext 0.2 v. C0.5 v to +3.8 v input voltage 4, 5 5 applies to pins designated as 5 v tolerant only. C0.5 v to +5.5 v output voltage swing C0.5 v to v ddext + 0.5 v junction temperature while biased +125c storage temperature range C65c to +150c table 18. maximum duty cycle for input transient voltage 1 1 applies to all signal pins with the exception of clkin, mxi, mxo, mlf, vrout1C0, xtal, rtxi, and rtxo. v in min (v) 2 2 the individual values cannot be combined for analysis of a single instance of overshoot or undershoot. the worst case observed value must fall within one of the voltages specified and the total dura tion of the overshoot or undershoot (exceeding the 100% case) must be less th an or equal to the corresponding duty cycle. v in max (v) 2 maximum duty cycle 3 3 duty cycle refers to the percentage of time the signal exceeds the value for the 100% case. the is equivalent to the meas ured duration of a single instance of overshoot or unders hoot as a percentage of the period of occurrence. C0.50 +3.80 100% C0.70 +4.00 40% C0.80 +4.10 25% C0.90 +4.20 15% C1.00 +4.30 10% figure 10. product information on package table 19. package brand information 1 1 non automotive only. for branding in formation specific to automotive products, contact analog devices inc. brand key field description ttemperature range pp package type z rohs compliant part ccc see ordering guide vvvvvv.xw assembly lot code n.n silicon revision # rohs compliant designation yyww date code esd (electrostatic discharge) sensitive device. charged devices and circuit boards can discharge without detection. although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy esd. therefore, proper esd precautions should be taken to avoid performance degradation or loss of functionality. vvvvvv.x n.n tppzccc ADSP-BF539 a #yyww country_of_origin b
ADSP-BF539 / ADSP-BF539f rev. f | page 31 of 60 | october 2013 timing specifications component specifications are subject to change with pcn notice. clock and reset timing table 20 and figure 11 describe clock and reset operations. per absolute maximum ratings on page 30 , combinations of clkin and clock multipliers must not select core/peripheral clocks that exceed maximum operating conditions. table 20. clock and reset timing parameter min max unit timing requirement s f ckin clkin frequency (commercial/ industrial models) 1, 2, 3, 4 10 50 mhz clkin frequency (automotive models) 1, 2, 3, 4 10 50 mhz t ckinl clkin low pulse 1 8ns t ckinh clkin high pulse 1 8ns t wrst reset asserted pulse width low 5 11 t ckin ns t noboot reset deassertion to first external access delay 6 3 t ckin 5 t ckin ns 1 applies to pll bypass mode and pll nonbypass mode. 2 combinations of the clkin frequency and the pl l clock multiplier must no t exceed the allowed f vco , f cclk , and f sclk settings discussed in table 12 on page 26 through table 16 on page 29 . 3 the t ckin period (see figure 11 ) equals 1/f ckin . 4 if the df bit in the pll_ctl register is set, the minimum f ckin specification is 24 mhz for commercial/industri al models and 28 mhz for automotive models. 5 applies after power-up se quence is complete. see table 21 and figure 12 for power-up reset timing. 6 applies when processor is configured in no boot mode (bmode2-0 = b#000). figure 11. clock and reset timing table 21. power-up reset timing parameter min max unit timing requirement t rst_in_pwr reset deasserted after the v ddint , v ddext , v ddrtc , mpivdd, mxevdd, and clkin pins are stable and within specification 3500 t ckin ns in figure 12 , v dd_supplies is v ddint , v ddext , v ddrtc , mpivdd, mxevdd figure 12. power -up reset timing clkin t wrst t ckin t ckinl t ckinh reset t noboot reset t rst_in_pwr clkin v dd_supplies
rev. f | page 32 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f asynchronous memory read cycle timing table 22 and table 23 on page 33 and figure 13 and figure 14 on page 33 describe asynchronous memory read cycle opera- tions for synchronous and for asynchronous ardy. table 22. asynchronous memory read cycle timing with synchronous ardy parameter min max unit timing requirements t sdat data15C0 setup before clkout 2.1 ns t hdat data15C0 hold after clkout 0.8 ns t sardy ardy setup before the falling edge of clkout 4.0 ns t hardy ardy hold after the falling edge of clkout 0.0 ns switching characteristics t do output delay after clkout 1 6.0 ns t ho output hold after clkout 1 0.8 ns 1 output pins include ams3C0 , abe1C0 , addr19C1, aoe , are . figure 13. asynchronous memory read cycle timing with synchronous ardy t sardy t hardy t sardy t hardy setup 2 cycles programmed read access 4 cycles access extended 3 cycles hold 1 cycle t do t ho t do t sdat t hdat clkout amsx abe1C0 addr19C1 aoe are ardy data 15C0 t ho
ADSP-BF539 / ADSP-BF539f rev. f | page 33 of 60 | october 2013 table 23. asynchronous memory read cy cle timing with asynchronous ardy parameter min max unit timing requirements t sdat data15C0 setup before clkout 2.1 ns t hdat data15C0 hold after clkout 0.8 ns t danr ardy negated delay from amsx asserted 1 (s + ra C 2) t sclk ns t haa ardy asserted hold after are negated 0.0 ns switching characteristics t do output delay after clkout 2 6.0 ns t ho output hold after clkout 2 0.8 ns 1 s = number of programmed setup cycles, ra = number of programmed read access cycles. 2 output pins include ams3C0 , abe1C0 , addr19C1, aoe , are . figure 14. asynchronous memory read cycle timing with asynchronous ardy setup 2 cycles programmed read access 4 cycles access extended 3 cycles hold 1 cycle t do t ho t do t danr t sdat t hdat clkout amsx abe1C0 addr19C1 aoe are ardy data 15C0 t ho t haa
rev. f | page 34 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f asynchronous memory write cycle timing table 24 and table 25 and figure 15 and figure 16 describe asynchronous memory write cycl e operations for synchronous and for asynchronous ardy. table 24. asynchronous memory write cycle timing with synchronous ardy parameter min max unit timing requirements t sardy ardy setup before the falling edge of clkout 4.0 ns t hardy ardy hold after the falling edge of clkout 0.0 ns switching characteristics t ddat data15C0 disable after clkout 6.0 ns t endat data15C0 enable after clkout 1.0 ns t do output delay after clkout 1 6.0 ns t ho output hold after clkout 1 0.8 ns 1 output pins include ams3C0 , abe1C0 , addr19C1, data15C0, aoe, awe . figure 15. asynchronous me mory write cycle timing with synchronous ardy setup 2 cycles programmed write access 2 cycles access extend 1 cycle hold 1 cycle t do t ho clkout amsx abe1C0 addr19C1 awe data 15C0 t do t sardy t ddat t endat t ho t hardy t hardy ardy t sardy
ADSP-BF539 / ADSP-BF539f rev. f | page 35 of 60 | october 2013 table 25. asynchronous memory write cycle timing with asynchronous ardy parameter min max unit timing requirements t danr ardy negated delay from amsx asserted 1 (s + wa C 2) t sclk ns t haa ardy asserted hold after are negated 0.0 ns switching characteristics t ddat data15C0 disable after clkout 6.0 ns t endat data15C0 enable after clkout 1.0 ns t do output delay after clkout 2 6.0 ns t ho output hold after clkout 2 0.8 ns 1 s = number of programmed setup cycles, wa = n umber of programmed write access cycles. 2 output pins include ams3C0 , abe1C0 , addr19C1, data15C0, aoe, awe . figure 16. asynchronous memory write cycle timing with asynchronous ardy setup 2 cycles programmed write access 2 cycles access extended 2 cycles hold 1 cycle t do t ho clkout amsx abe1C0 addr19C1 awe ardy data 15C0 t do t ddat t endat t ho t danw t haa
rev. f | page 36 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f sdram interface timing table 26. sdram interface timing parameter min max unit timing requirement s t ssdat data setup before clkout 2.1 ns t hsdat data hold after clkout 0.8 ns switching characteristics t sclk clkout period 1 1 sdram timing for t junction = 125c is limited to 100 mhz. 7.5 ns t sclkh clkout width high 2.5 ns t sclkl clkout width low 2.5 ns t dcad command, addr, data delay after clkout 2 2 command pins include: sras , scas , swe , sdqm, sms , sa10, scke. 6.0 ns t hcad command, addr, data hold after clkout 2 0.8 ns t dsdat data disable after clkout 6.0 ns t ensdat data enable after clkout 1.0 ns figure 17. sdram interface timing t sclk clkout t sclkl t sclkh t ssdat t hsdat t ensdat t dcad t dsdat t hcad t dcad t hcad data (in) data (out) command, address (out) note: command = sras , scas , swe , sdqm, sms , sa10, scke.
ADSP-BF539 / ADSP-BF539f rev. f | page 37 of 60 | october 2013 external port bus request and grant cycle timing table 27 and table 28 and figure 18 and figure 19 describe external port bus request and grant cycle operations for syn- chronous and for asynchronous br . table 27. external port bus request and grant cycle timing with synchronous br parameter min max unit timing requirements t bs br setup to falling edge of clkout 4.6 ns t bh falling edge of clkout to br deasserted hold time 1.0 ns switching characteristics t sd clkout low to amsx , address, and are /awe disable 4.5 ns t se clkout low to amsx , address, and are /awe enable 4.5 ns t dbg clkout high to bg high setup 4.0 ns t ebg clkout high to bg deasserted hold time 4.0 ns t dbh clkout high to bgh high setup 4.0 ns t ebh clkout high to bgh deasserted hold time 4.0 ns figure 18. external port bus request and grant cycle timing with synchronous br amsx clkout bg bgh br addr 19-1 abe1-0 t bh t bs t sd t se t sd t sd t se t se t ebg t dbg t ebh t dbh awe are
rev. f | page 38 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f table 28. external port bus request and grant cycle timing with asynchronous br parameter min max unit timing requirement t wbr br pulse width 2 t sclk ns switching characteristics t sd clkout low to amsx , address, and are /awe disable 4.5 ns t se clkout low to amsx , address, and are /awe enable 4.5 ns t dbg clkout high to bg high setup 3.6 ns t ebg clkout high to bg deasserted hold time 3.6 ns t dbh clkout high to bgh high setup 3.6 ns t ebh clkout high to bgh deasserted hold time 3.6 ns figure 19. external port bus request and gr ant cycle timing with asynchronous br amsx clkout bg bgh br addr 19-1 abe1-0 t sd t se t sd t sd t se t se t ebg t dbg t ebh t dbh awe are t wbr
ADSP-BF539 / ADSP-BF539f rev. f | page 39 of 60 | october 2013 parallel peripheral interface timing table 29 and figure 20 , figure 21 , figure 22 , and figure 23 describe parallel peripheral interface operations. table 29. parallel peripheral interface timing parameter min max unit timing requirements t pclkw ppi_clk width 6.0 ns t pclk ppi_clk period 1 15.0 ns t sfspe external frame sync setup before ppi_clk 5.0 ns t hfspe external frame sync hold after ppi_clk 1.0 ns t sdrpe receive data setup before ppi_clk 2.0 ns t hdrpe receive data hold after ppi_clk 4.0 ns switching characteristicsgp output and frame capture modes t dfspe internal frame sync delay after ppi_clk 10.0 ns t hofspe internal frame sync hold after ppi_clk 0.0 ns t ddtpe transmit data delay after ppi_clk 10.0 ns t hdtpe transmit data hold after ppi_clk 0.0 ns 1 ppi_clk frequency cannot exceed f sclk /2. figure 20. ppi gp rx mode with internal frame sync timing figure 21. ppi gp rx mode with external frame sync timing t hdrpe t sdrpe t hofspe frame sync driven data sampled ppi_data ppi_clk ppi_fs1/2 t dfspe t pclk t pclkw t pclk t sfspe data sampled / frame sync sampled data sampled / frame sync sampled ppi_data ppi_clk ppi_fs1/2 t hfspe t hdrpe t sdrpe t pclkw
rev. f | page 40 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f figure 22. ppi gp tx mode with external frame sync timing figure 23. ppi gp tx mode with internal frame sync timing t hdtpe t sfspe data driven / frame sync sampled ppi_data ppi_clk ppi_fs1/2 t hfspe t ddtpe t pclk t pclkw t hofspe frame sync driven data driven ppi_data ppi_clk ppi_fs1/2 t dfspe t ddtpe t hdtpe t pclk t pclkw data driven
ADSP-BF539 / ADSP-BF539f rev. f | page 41 of 60 | october 2013 serial ports timing table 30 through table 33 and figure 24 through figure 27 describe serial port operations. table 30. serial portsexternal clock parameter min max unit timing requirements t sfse tfsx/rfsx setup before tsclkx/rsclk x (externally generated tfsx/rfsx) 1 3.0 ns t hfse tfsx/rfsx hold after tsclkx/rsclk x (externally generated tfsx/rfsx) 1 3.0 ns t sdre receive data setup before rsclkx 1 3.0 ns t hdre receive data hold after rsclkx 1 3.0 ns t sclkew tsclkx/rsclkx width 4.5 ns t sclke tsclkx/rsclkx period 15.0 ns t sudte start-up delay from sport enable to first external tfsx 2 4.0 t sclke ns t sudre start-up delay from sport enable to first external rfsx 2 4.0 t sclke ns switching characteristics t dfse tfsx/rfsx delay after tsclkx/rsclk x (internally generated tfsx/rfsx) 3 10.0 ns t hofse tfsx/rfsx hold after tsclkx/rsclk x (internally generated tfsx/rfsx) 3 0.0 ns t ddte transmit data delay after tsclkx 3 10.0 ns t hdte transmit data hold after tsclkx 3 0.0 ns 1 referenced to sample edge. 2 verified in design but untested. after bein g enabled, the serial port requires exte rnal clock pulsesbefore the first external frame sync edgeto initia lize the serial port. 3 referenced to drive edge. table 31. serial portsinternal clock parameter min max unit timing requirements t sfsi tfsx/rfsx setup before tsclkx/rsclk x (externally generated tfsx/rfsx) 1 9.0 ns t hfsi tfsx/rfsx hold after tsclkx/rsclk x (externally generated tfsx/rfsx) 1 C1.5 ns t sdri receive data setup before rsclkx 1 9.0 ns t hdri receive data hold after rsclkx 1 C1.5 ns switching characteristics t dfsi tfsx/rfsx delay after tsclkx/rsclk x (internally generated tfsx/rfsx) 2 3.5 ns t hofsi tfsx/rfsx hold after tsclkx/rsclk x (internally generated tfsx/rfsx) 2 C1.0 ns t ddti transmit data delay after tsclkx 2 3.0 ns t hdti transmit data hold after tsclkx 2 C2.0 ns t sclkiw tsclkx/rsclkx width 4.5 ns 1 referenced to sample edge. 2 referenced to drive edge.
rev. f | page 42 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f figure 24. serial ports figure 25. serial port start up with external clock and frame sync t sdri rsclkx drx drive edge t hdri t sfsi t hfsi t dfsi t h ofsi t sclkiw data receiveinternal clock t sdre data receiveexternal clock rsclkx drx t hdre t sfse t hfse t dfse t sclkew t hofse t ddti t hdti tsclkx tfsx (input) dtx t sfsi t hfsi t sclkiw t dfsi t hofsi data transmitinternal clock t ddte t hdte tsclkx dtx t sfse t dfse t sclkew t hofse data transmitexternal clock sample edge drive edge sample edge drive edge sample edge drive edge sample edge t sclke t sclke t hfse tfsx (output) tfsx (input) tfsx (output) rfsx (input) rfsx (output) rfsx (input) rfsx (output) tsclkx (input) tfsx (input) rfsx (input) rsclkx (input) t sudte t sudre first tsclkx/rsclkx edge after sport enabled
ADSP-BF539 / ADSP-BF539f rev. f | page 43 of 60 | october 2013 table 32. serial portsenable and three-state parameter min max unit switching characteristics t dtene data enable delay fr om external tsclkx 1 0ns t ddtte data disable delay from external tsclkx 1, 2, 3 10.0 ns t dteni data enable delay from internal tsclkx 1 C2.0 ns t ddtti data disable delay from internal tsclkx 1, 2, 3 3.0 ns 1 referenced to drive edge. 2 applicable to multi channel mode only. 3 tsclkx is tied to rsclkx. figure 26. enable and three-state table 33. external late frame sync parameter min max unit switching characteristics t ddtlfse data delay from late external tfsx or external rfsx in multichannel mode, mfd = 0 1, 2 10.0 ns t dtenlfs data enable from late fs or multichannel mode, mfd = 0 1, 2 0ns 1 in multichannel mode, tfsx en able and tfsx valid follow t dtenlfs and t ddtlfse . 2 if external rfsx/tfsx setu p to rsclkx/tsclkx > t sclke /2, then t ddtte/i and t dtene/i apply; otherwise t ddtlfse and t dtenlfs apply. tsclkx dtx drive edge t ddtte/i t dtene/i drive edge
rev. f | page 44 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f figure 27. external late frame sync rsclkx rfsx dtx drive edge drive edge sample edge external rfsx in multi-channel mode 1st bit t dtenlfse t ddtlfse tsclkx tfsx dtx drive edge drive edge sample edge late external tfsx 1st bit t ddtlfse
ADSP-BF539 / ADSP-BF539f rev. f | page 45 of 60 | october 2013 serial peripheral interface portsmaster timing table 34 and figure 28 describe spi ports master operations. table 34. serial peripheral interface (spi) portsmaster timing parameter min max unit timing requirements t sspidm data input valid to sckx edge (data input setup) 9.0 ns t hspidm sckx sampling edge to data input invalid C1.5 ns switching characteristics t sdscim spixsely low to first sckx edge 2t sclk C1.5 ns t spichm serial clock high period 2t sclk C1.5 ns t spiclm serial clock low period 2t sclk C1.5 ns t spiclk serial clock period 4t sclk C1.5 ns t hdsm last sckx edge to spixsely high 2t sclk C1.5 ns t spitdm sequential transfer delay 2t sclk C1.5 ns t ddspidm sckx edge to data out valid (data out delay) 5 ns t hdspidm sckx edge to data out invalid (data out hold) C1.0 ns figure 28. serial peripheral interface (spi) portsmaster timing t sdscim t spiclk t hdsm t spitdm t spiclm t spichm t hdspidm t hspidm t sspidm spixsely (output) spixsck (output) spixmosi (output) spixmiso (input) spixmosi (output) spixmiso (input) cpha = 1 cpha = 0 t ddspidm t hspidm t sspidm t hdspidm t ddspidm
rev. f | page 46 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f serial peripheral interface portsslave timing table 35 and figure 29 describe spi ports slave operations. table 35. serial peripheral interface (spi) portsslave timing parameter min max unit timing requirements t spichs serial clock high period 2t sclk C1.5 ns t spicls serial clock low period 2t sclk C1.5 ns t spiclk serial clock period 4t sclk ns t hds last sckx edge to spixss not asserted 2t sclk C1.5 ns t spitds sequential transfer delay 2t sclk C1.5 ns t sdsci spixss assertion to first sckx edge 2t sclk C1.5 ns t sspid data input valid to sckx edge (data input setup) 2.0 ns t hspid sckx sampling edge to data input invalid 2.0 ns switching characteristics t dsoe spixss assertion to data out active 0 8 ns t dsdhi spixss deassertion to data high impedance 0 8 ns t ddspid sckx edge to data out valid (data out delay) 10 ns t hdspid sckx edge to data out invalid (data out hold) 0 ns figure 29. serial peripheral interface (spi) portsslave timing t spiclk t hds t spitds t sdsci t spicls t spichs t dsoe t ddspid t ddspid t dsdhi t hdspid t sspid t dsdhi t hdspid t dsoe t hspid t sspid t ddspid spixss (input) spixsck (input) spixmiso (output) spixmosi (input) spixmiso (output) spixmosi (input) cpha = 1 cpha = 0 t hspid
ADSP-BF539 / ADSP-BF539f rev. f | page 47 of 60 | october 2013 general-purpose port timing table 36 and figure 30 describe general-purpose operations. universal asynchronous receiver-transmitter (uart) portsreceive and transmit timing for information on the uart po rt receive and transmit opera- tions, see the ADSP-BF539 hardware reference manual . mxvr timing table 37 and table 38 describe the mxvr timing requirements. table 36. general-purpose port timing parameter min max unit timing requirement t wfi gp port pin input pulse width t sclk + 1 ns switching characteristic t gpod gp port pin output delay from clkout low 6 ns figure 30. general-purpose port cycle timing clkout gpio output gpio input t wfi t gpod table 37. mxvr timingmxi center frequency requirements parameter f s = 38 khz f s = 44.1 khz f s = 48 khz unit f mxi mxi center frequency 38.912 45.1584 49.152 mhz table 38. mxvr timing mxi clock requirements parameter min max unit timing requirement s fs mxi mxi clock frequency stability C50 +50 ppm ft mxi mxi frequency tolerance over temperature C300 +300 ppm dc mxi mxi clock duty cycle 40 60 %
rev. f | page 48 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f timer clock timing table 39 and figure 31 describe timer clock timing. timer cycle timing table 40 and figure 32 describe timer expired operations. the input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input fre- quency of f sclk /2 mhz. table 39. timer clock timing parameter min max unit switching characteristic t todp timer output update delay after ppi_clk high 12 ns figure 31. timer clock timing ppi_clk tmrx output t todp table 40. timer cycle timing v ddext = 1.8 v v ddext = 2.5 v/3.3 v parameter min max min max unit timing characteristics t wl timer pulse width low 1 1 t sclk 1 t sclk ns t wh timer pulse width high 1 1 t sclk 1 t sclk ns t tis timer input setup time before clkout low 2 8.0 6.5 ns t tih timer input hold time after clkout low 2 1.5 1.5 ns switching characteristic s t hto timer pulse width output 1 t sclk (2 32 C1) t sclk 1 t sclk (2 32 C1) t sclk ns t tod timer output update delay after clkout high 7.5 6.5 ns 1 the minimum pulse widths apply for tmrx input pins in width capture and external clock mo des. they also apply to the pf1 or ppi _clk input pins in pwm output mode. 2 either a valid setup and hold time or a valid pulse width is suff icient. there is no need to re synchronize programmable flag in puts. figure 32. timer pw m_out cycle timing clkout tmrx output tmrx input t tis t tih t wh ,t wl t tod t hto
ADSP-BF539 / ADSP-BF539f rev. f | page 49 of 60 | october 2013 jtag test and emulation port timing table 41 and figure 33 describe jtag port operations. table 41. jtag port timing parameter min max unit timing requirements t tck tck period 20 ns t stap tdi, tms setup before tck high 4 ns t htap tdi, tms hold after tck high 4 ns t ssys system inputs setup before tck high 1 4ns t hsys system inputs hold after tck high 1 6ns t trstw trst pulse width 2 (measured in tck cycles) 4 tck switching characteristics t dtdo tdo delay from tck low 10 ns t dsys system outputs delay after tck low 3 012ns 1 system inputs = ardy, bmode1C0, br , data15C0, nmi , pf15C0, ppi_clk, ppi3C0, scl1C0, sda1C0, mtxon , mrxon , mmclk, mbclk, mfs, mtx, mrx, spi1ss , spi1sel1 , sck2C0, miso2C0, mosi2C0, spi2ss , spi2sel1 , rx2C0, tx2C1, dr0pri, dr0sec, dr1pri, dr1sec, dt2pri, dt2sec, dr2pri, dr2sec, tsclk3C0, rsclk3C0, tfs3C0, rfs3C0, dt3pri, dt3sec, dr3pri, dr3sec, cantx, canrx, reset , and tmr2C0. 2 50 mhz maximum 3 system outputs = ams , aoe , are , awe , abe , bg , data15C0, pf15C0, ppi3C0, mtxon , mmclk, mbclk, mfs, mtx, spi1ss , spi1sel1 , sck2C0, miso2C0, mosi2C0, spi2ss , spi2sel1 , rx2C1, tx2C0, dt2pri, dt2sec, dr2pri, dr2sec, dt3pri, dt3sec, dr3pri, dr3sec, ts clk3C0, tfs3C0, rsclk3C0, rfs3C0, clkout, cantx, sa10, scas , scke, sms , sras , swe , and tmr2C0. figure 33. jtag port timing tck tms tdi tdo system inputs system outputs t tck t stap t htap t dtdo t ssys t hsys t dsys
rev. f | page 50 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f output drive currents the following figures show typical current-voltage characteris- tics for the output drivers of the ADSP-BF539/ADSP-BF539f processor. the curves represent the current drive capability of the output drivers as a fu nction of output voltage. figure 34. drive current a (low v ddext ) figure 35. drive current a (high v ddext ) 0 s o u r c e c u r r en t ( m a ) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 100 60 40 - 80 - 60 - 40 - 20 120 20 80 - 100 v ddext = 2.75v v oh v ol 0 s ou r c e c u r r e n t ( m a ) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 150 100 50 - 150 - 100 - 50 v ol v oh 4.0 v ddext =3.0v v ddext =3.3v v ddext =3.6v figure 36. drive current b (low v ddext ) figure 37. drive current b (hig v ddext ) figure 38. drive current c (low v ddext ) 0 s o u rc e c u r re n t (m a ) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 150 100 - 150 v ol v oh - 100 - 50 50 v ddext =2.75v 0 s o u rc e c u r r e n t (m a ) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 150 100 50 - 200 - 150 v ol v oh 4.0 - 100 - 50 200 v ddext =3.0v v ddext =3.3v v ddext =3.6v 0 s o ur c e c u r re n t (m a ) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 80 60 - 60 v ol v oh - 40 - 20 40 20 v ddext =2.75v
ADSP-BF539 / ADSP-BF539f rev. f | page 51 of 60 | october 2013 figure 39. drive current c (high v ddext ) figure 40. drive current d (low v ddext ) figure 41. drive current d (high v ddext ) 0 s o u rc e c u r r e n t (m a ) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 80 60 40 - 80 - 60 v ol v oh 4.0 - 40 - 20 100 20 v ddext =3.0v v ddext =3.3v v ddext =3.6v 0 so u r c e cu r r e nt (m a) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 80 60 40 - 80 - 60 v ol v oh - 40 - 20 100 20 v ddext =2.75v 0 s o u r c e c ur r e n t (m a ) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 100 50 - 150 v ol v oh 4.0 - 100 - 50 150 v ddext =3.0v v ddext =3.3v v ddext =3.6v figure 42. drive current e (low v ddext ) figure 43. drive current e (hig v ddext ) - 40 so u r c e c u r r e n t ( m a) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 - 60 0 - 10 v ol - 20 - 30 - 50 v ddext =2.75v - 40 s o u rc e c u r r e n t (m a ) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 - 10 - 20 - 80 - 70 v ol 4.0 - 60 - 50 - 30 v ddext =3.0v v ddext =3.3v v ddext =3.6v
rev. f | page 52 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f test conditions all timing parameters appearing in this data sheet were mea- sured under the conditions described in this section. figure 44 shows the measurement point for ac measurements (except out- put enable/disable). the measurement point v meas is 1.5 v for v ddext (nominal) = 3.3 v. output enable time measurement output pins are considered to be enabled when they have made a transition from a high impedanc e state to the point when they start driving. the output enable time t ena is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown on the right side of figure 45 on page 52 . the time t ena_measured is the interval, from when the reference signal switches, to when the output voltage reaches v trip (high) or v trip (low). v trip (high) is 2.0 v and v trip (low) is 1.0 v for v ddext (nominal) = 3.3 v. time t trip is the interval from when the output starts driving to when the output reaches the v trip (high) or v trip (low) trip voltage. time t ena is calculated as shown in the equation: if multiple pins (such as the da ta bus) are enab led, the measure- ment value is that of the first pin to start driving. output disable time measurement output pins are considered to be disabled when they stop driv- ing, go into a high impedance stat e, and start to decay from their output high or low voltage. the output disable time t dis is the difference between t dis_measured and t decay as shown on the left side of figure 45 . the time for the voltage on the bus to decay by ? v is dependent on the capacitive load c l and the load current i l . this decay time can be approximated by the equation: the time t decay is calculated with test loads c l and i l , and with ? v equal to 0.5 v for v ddext (nominal) = 3.3 v. the time t dis+_measured is the interval from when the reference signal switches, to when the output voltage decays ? v from the measured output high or output low voltage. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose ? v to be the difference between the ADSP-BF539/ADSP-BF539f processor output voltage and the input threshold for the device requiring the hold time. c l is the total bus capacitance (per data line), and i l is the total leakage or th ree-state current (per data line). the hold time is t decay plus the various output disable times as specified in the timing specifications on page 31 (for example, t dsdat for an sdram write cycle as shown in table 26 on page 36 ). capacitive loading output delays and holds are based on standard capacitive loads: 30 pf on all pins (see figure 46 ). v load is 1.5 v for v ddext (nominal) = 3.3 v. figure 47 on page 53 through figure 56 on page 54 show how output rise and fall times vary with capaci- tance. the delay and hold specifications given should be de- rated by a factor derived from these figures. the graphs in these figures may not be linear outside the ranges shown. figure 44. voltage reference levels for ac measurements (except output enable/disable) input or output v meas v meas t ena t ena_measured t trip ? = t dis t dis_measured t decay ? = t decay c l v ? ?? i l ? = figure 45. output enable/disable figure 46. equivalent device loading for ac measurements (includes all fixtures) reference signal t dis output starts driving v oh (measured) v v ol (measured) + v t dis_measured v oh (measured) v ol (measured) v trip (high) v oh (measured ) v ol (measured) high impedance state output stops driving t ena t decay t ena_measured t trip v trip (low) t1 zo = 50 : (impedance) td = 4.04 1.18 ns 2pf tester pin electronics 50 : 0.5pf 70 : 400 : 45 : 4pf notes: the worst case transmission line delay is shown and can be used for the output timing analysis to refelect the transmission line effect and must be considered. the transmission line (td) is for load only and does not affect the data sheet timing specifications. analog devices recommends using the ibis model timing for a given system requirement. if necessary, a system may incorporate external drivers to compensate for any timing differences. v load dut output 50 :
ADSP-BF539 / ADSP-BF539f rev. f | page 53 of 60 | october 2013 figure 47. typical rise and fall times (10% to 90%) vs. load capacitance for driver a at v ddext = 2.7 v (min) figure 48. typical rise and fall times (10% to 90%) vs. load capacitance for driver a at v ddext = 3.65 v (max) figure 49. typical rise and fall times (10% to 90%) vs. load capacitance for driver b at v ddext = 2.7 v (min) load capacitance (pf) rise time rise and fall time ns (10% to 90%) 14 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time load capacitance (pf) rise time rise and fall time ns (10% to 90%) 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time load capacitance (pf) rise time rise and fall time ns (10% to 90%) 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time figure 50. typical rise and fall times (10% to 90%) vs. load capacitance for driver b at v ddext = 3.65 v (max) figure 51. typical rise and fall times (10% to 90%) vs. load capacitance for driver c at v ddext = 2.7 v (min) figure 52. typical rise and fall times (10% to 90%) vs. load capacitance for driver c at v ddext = 3.65 v (max) load capacitance (pf) rise time rise and fall time ns (10% to 90%) 10 9 8 7 6 5 4 3 2 1 0 0 50 100 150 200 250 fall time load capacitance (pf) rise time rise and fall time ns (10% to 90%) 25 30 20 15 10 5 0 0 50 100 150 200 250 fall time load capacitance (pf) rise time rise and fall time ns (10% to 90%) 20 18 16 14 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time
rev. f | page 54 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f figure 53. typical rise and fall times (10% to 90%) vs. load capacitance for driver d at v ddext = 2.7 v (min) figure 54. typical rise and fall times (10% to 90%) vs. load capacitance for driver d at v ddext = 3.65 v (max) figure 55. typical fall time (10% to 90%) vs. load capacitance for driver e at v ddext = 2.7 v (min) load capacitance (pf) rise time rise and fall time ns (10% to 90%) 18 16 14 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time load capacitance (pf) rise time rise and fall time ns (10% to 90%) 14 12 10 8 6 4 2 0 0 50 100 150 200 250 fall time load capacitance (pf) fall time ns (10% to 90%) 132 128 124 120 116 108 0 50 100 150 200 250 fall time 112 figure 56. typical fall time (10% to 90%) vs. load capacitance for driver e at v ddext = 3.65 v (max) load capacitance (pf) fall time ns (10% to 90%) 124 120 116 112 108 100 0 50 100 150 200 250 fall time 104
ADSP-BF539 / ADSP-BF539f rev. f | page 55 of 60 | october 2013 thermal characteristics to determine the junction te mperature on the application printed circuit board use where: t j = junction temperature (c) t case = case temperature (c) meas ured by customer at top cen- ter of package. ? jt = from table 42 or table 43 p d = power dissipation (see electrical characteristics on page 27 for the method to calculate p d ) values of ? ja are provided for packag e comparison and printed circuit board design considerations. ? ja can be used for a first order approximation of t j by the equation: where: t a = ambient temperature (c) values of ? jc are provided for package comparison and printed circuit board design considerations when an external heatsink is required. values of ? jb are provided for packag e comparison and printed circuit board design considerations. in table 42 and table 43 , airflow measurements comply with jedec standards jesd51-2 and je sd51-6, and the junction-to- board measurement complies wi th jesd51-8. th e junction-to- case measurement complies with mil-std-883 (method 1012.1). all measurements use a 2s2p jedec test board. table 42. thermal characteristics bc-316 without flash parameter condition typical unit ? ja 0 linear m/s air flow 25.4 c/w ? jma 1 linear m/s air flow 22.8 c/w ? jma 2 linear m/s air flow 22.0 c/w ? jc 6.7 c/w ? jt 0 linear m/s air flow 0.18 c/w ? jt 1 linear m/s air flow 0.38 c/w ? jt 2 linear m/s air flow 0.40 c/w table 43. thermal characteristics bc-316 with flash parameter condition typical unit ? ja 0 linear m/s air flow 24.3 c/w ? jma 1 linear m/s air flow 21.8 c/w ? jma 2 linear m/s air flow 21.0 c/w ? jc 6.3 c/w ? jt 0 linear m/s air flow 0.17 c/w ? jt 1 linear m/s air flow 0.36 c/w ? jt 2 linear m/s air flow 0.38 c/w t j t case ? jt p d ? ?? + = t j t a ? ja p d ? ?? + =
rev. f | page 56 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f 316-ball csp_bga ball assignment figure 57 lists the top view of the csp_bga ball assignment. figure 58 lists the bottom view of the csp_bga ball assignment. table 44 on page 57 lists the csp_bga ball assignment by ball number. table 45 on page 58 lists the csp_bga ball assign- ment by signal. figure 57. 316-ball csp_bga ba ll assignment (top view) a b c d e f g h j k l m n p r u v w y t 20 19 18 17 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 a1 ball vddint vddext gnd i/o vddrtc vroutx nc note: h18 and y14 are nc for ADSP-BF539 and i/o ( fce and freset ) for ADSP-BF539f figure 58. 316-ball csp_bga ba ll assignment (bottom view) vddint vddext gnd i/o vddrtc vroutx nc a b c d e f g h j k l m n p r u v w y t 20191817 151413121110987654321 16 a1 ball note: h18 and y14 are nc for ADSP-BF539 and i/o ( fce and freset ) for ADSP-BF539f
ADSP-BF539 / ADSP-BF539f rev. f | page 57 of 60 | october 2013 table 44. 316-ball csp_bga ball assignme nt (numerically by ball number) ball no. signal ball no. signal ball no. signal ball no. signal ball no. signal ball no. signal ball no. signal a1 gnd c7 spi2sel1 f8 gnd j12 gnd m19 abe0 t3 gnd w1 tck a2 pf10 c8 spi2ss f9 gnd j13 gnd m20 abe1 t7 v ddext w2 gnd a3 pf11 c9 mosi2 f10 gnd j14 gnd n1 tfs0 t8 v ddext w3 data15 a4 ppi_clk c10 miso2 f11 gnd j18 ams0 n2 dr0pri t9 v ddext w4 data13 a5 ppi0 c11 sck2 f12 gnd j19 ams2 n3 gnd t10 v ddext w5 data11 a6 ppi2 c12 mpivdd f13 gnd j20 sa10 n7 v ddext t11 v ddext w6 data9 a7 pf15 c13 spi1sel1 f14 gnd k1 rfs1 n8 gnd t12 v ddint w7 data7 a8 pf13 c14 miso1 f18 dt3pri k2 tmr2 n9 gnd t13 v ddint w8 data5 a9 v ddrtc c15 spi1ss f19 mrx k3 gp n10 gnd t14 v ddint w9 data3 a10 rtxo c16 mosi1 f20 mfs k7 gnd n11 gnd t18 rfs3 w10 data1 a11 rtxi c17 sck1 g1 sck0 k8 gnd n12 gnd t19 addr7 w11 rsclk2 a12 gnd c18 gnd g2 mosi0 k9 gnd n13 gnd t20 addr8 w12 dr2pri a13 clkin c19 mmclk g3 dt0sec k10 gnd n14 v ddint u1 trst w13 dt2pri a14 xtal c20 scke g7 gnd k11 gnd n18 dt3sec u2 tms w14 rx2 a15 mlf d1 pf4 g8 gnd k12 gnd n19 addr1 u3 gnd w15 tx2 a16 mxo d2 pf5 g9 gnd k13 gnd n20 addr2 u7 v ddext w16 addr18 a17 mxi d3 dt1sec g10 gnd k14 gnd p1 tsclk0 u8 v ddext w17 addr15 a18 mrxon d7 gnd g11 gnd k18 ams3 p2 rfs0 u9 v ddext w18 addr13 a19 vrout1 d8 gnd g12 gnd k19 ams1 p3 gnd u10 v ddext w19 gnd a20 gnd d9 gnd g13 gnd k20 aoe p7 v ddext u11 v ddext w20 addr14 b1 pf8 d10 gnd g14 gnd l1 rsclk1 p8 gnd u12 v ddint y1 gnd b2 gnd d11 gnd g18 br l2 tmr1 p9 gnd u13 v ddint y2 tdo b3 pf9 d12 gnd g19 clkout l3 gnd p10 gnd u14 v ddint y3 data14 b4 pf3 d13 gnd g20 sras l7 gnd p11 gnd u18 rsclk3 y4 data12 b5 ppi1 d14 gnd h1 dt1pri l8 gnd p12 gnd u19 addr9 y5 data10 b6 ppi3 d18 gnd h2 tsclk1 l9 gnd p13 gnd u20 addr10 y6 data8 b7 pf14 d19 mbclk h3 dr1sec l10 gnd p14 v ddint v1 tdi y7 data6 b8 pf12 d20 sms h7 gnd l11 gnd p18 dr3sec v2 gnd y8 data4 b9 scl0 e1 pf1 h8 gnd l12 gnd p19 addr3 v3 gnd y9 data2 b10 sda0 e2 pf2 h9 gnd l13 gnd p20 addr4 v4 bmode1 y10 data0 b11 canrx e3 gnd h10 gnd l14 gnd r1 tx0 v5 bmode0 y11 rfs2 b12 cantx e7 gnd h11 gnd l18 tsclk3 r2 rsclk0 v6 gnd y12 tsclk2 b13 nmi e8 gndh12gndl19 are r3 gnd v7 v ddext y13 tfs2 b14 reset e9 gndh13gndl20 awe r7 v ddext v8 v ddext y14 freset b15 mxevdd e10 gnd h14 gnd m1 dt0pri r8 gnd v9 v ddext y15 scl1 b16 mxegnd e11 gnd h18 fce m2 tmr0 r9 gnd v10 v ddext y16 sda1 b17 mtxon e12 gnd h19 scas m3 gnd r10 gnd v11 v ddext y17 addr19 b18 gnd e13 gnd h20 swe m7 v ddext r11 gnd v12 v ddint y18 addr17 b19 gnd e14 gnd j1 tfs1 m8 gnd r12 gnd v13 dr2sec y19 addr16 b20 vrout0 e18 gnd j2 dr1pri m9 gnd r13 gnd v14 bg y20 gnd c1 pf6 e19 mtx j3 dr0sec m10 gnd r14 v ddint v15 bgh c2 pf7 e20 ardy j7 gnd m11 gnd r18 dr3pri v16 dt2sec c3 gnd f1 pf0 j8 gnd m12 gnd r19 addr5 v17 gnd c4 gnd f2 miso0 j9 gnd m13 gnd r20 addr6 v18 gnd c5 rx1 f3 gnd j10 gnd m14 v ddint t1 rx0 v19 addr11 c6 tx1 f7 gnd j11 gnd m18 tfs3 t2 emu v20 addr12
rev. f | page 58 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f table 45. 316-ball csp_bga ball assign ment (alphabetica lly by signal) signal ball no. signal ball no. signal ball no. signal ball no. signal ball no. signal ball no. signal ball no. abe0 m19 data8 y6 gnd e7 gnd k11 gnd v17 ppi2 a6 tsclk1 h2 abe1 m20 data9 w6 gnd e8 gnd k12 gnd v18 ppi3 b6 tsclk2 y12 addr1 n19 data10 y5 gnd e9 gnd k13 gnd w2 reset b14 tsclk3 l18 addr2 n20 data11 w5 gnd f8 gnd l13 gnd w19 rfs0 p2 tx0 r1 addr3 p19 data12 y4 gnd f9 gnd l14 gnd y1 rfs1 k1 tx1 c6 addr4 p20 data13 w4 gnd f10 gnd m3 gnd y20 rfs2 y11 tx2 w15 addr5 r19 data14 y3 gnd f11 gnd m8 gp k3 rfs3 t18 v ddext t8 addr6 r20 data15 w3 gnd f12 gnd m9 mbclk d19 rsclk0 r2 v ddext t9 addr7 t19 dr0pri n2 gnd f13 gnd m10 mfs f20 rsclk1 l1 v ddext t10 addr8 t20 dr0sec j3 gnd f14 gnd m11 miso0 f2 rsclk2 w11 v ddext t11 addr9 u19 dr1pri j2 gnd g7 gnd m12 miso1 c14 rsclk3 u18 v ddext u7 addr10 u20 dr1sec h3 gnd g8 gnd m13 miso2 c10 rtxi a11 v ddext u8 addr11 v19 dr2pri w12 gnd g9 gnd n3 mlf a15 rtxo a10 v ddext u9 addr12 v20 dr2sec v13 gnd e10 gnd k14 mmclk c19 rx0 t1 v ddext u10 addr13 w18 dr3pri r18 gnd e11 gnd l3 mosi0 g2 rx1 c5 v ddext u11 addr14 w20 dr3sec p18 gnd e12 gnd l7 mosi1 c16 rx2 w14 v ddext v7 addr15 w17 dt0pri m1 gnd e13 gnd l8 mosi2 c9 sa10 j20 v ddext m7 addr16 y19 dt0sec g3 gnd e14 gnd l9 mpivdd c12 scas h19 v ddext n7 addr17 y18 dt1pri h1 gnd e18 gnd l10 mrxon a18 sck0 g1 v ddext p7 addr18 w16 dt1sec d3 gnd f3 gnd l11 mrx f19 sck1 c17 v ddext r7 addr19 y17 dt2pri w13 gnd f7 gnd l12 mtx e19 sck2 c11 v ddext t7 ams0 j18 dt2sec v16 gnd g10 gnd n8 mtxon b17 scke c20 v ddext v8 ams1 k19 dt3pri f18 gnd g11 gnd n9 mxegnd b16 scl0 b9 v ddext v9 ams2 j19 dt3sec n18 gnd g12 gnd n10 mxevdd b15 scl1 y15 v ddext v10 ams3 k18 emu t2 gnd g13 gnd n11 mxi a17 sda0 b10 v ddext v11 aoe k20 fce h18 gnd g14 gnd n12 mxo a16 sda1 y16 v ddint m14 ardy e20 freset y14 gnd h7 gnd n13 nmi b13 sms d20 v ddint n14 are l19 gnd a1 gnd h8 gnd p3 pf0 f1 spi1sel1 c13 v ddint p14 awe l20 gnd a12 gnd h9 gnd p8 pf1 e1 spi1ss c15 v ddint r14 bg v14 gnd a20 gnd h10 gnd p9 pf2 e2 spi2sel1 c7 v ddint t12 bgh v15 gnd b2 gndh11 gndp10 pf3 b4 spi2ss c8 v ddint t13 bmode0 v5 gnd b18 gnd h12 gnd p11 pf4 d1 sras g20 v ddint t14 bmode1 v4 gnd b19 gnd h13 gnd p12 pf5 d2 swe h20 v ddint u12 br g18 gnd c3 gnd h14 gnd p13 pf6 c1 tck w1 v ddint u13 canrx b11 gnd c4 gnd j7 gnd r3 pf7 c2 tdi v1 v ddint u14 cantx b12 gnd c18 gnd j8 gnd r8 pf8 b1 tdo y2 v ddint v12 clkin a13 gnd d7 gnd j9 gnd r9 pf9 b3 tfs0 n1 v ddrtc a9 clkout g19 gnd d8 gnd j10 gnd r10 pf10 a2 tfs1 j1 vrout0 b20 data0 y10 gnd d9 gnd j11 gnd r11 pf11 a3 tfs2 y13 vrout1 a19 data1 w10 gnd d10 gnd j12 gnd r12 pf12 b8 tfs3 m18 xtal a14 data2 y9 gnd d11 gnd j13 gnd r13 pf13 a8 tmr0 m2 data3 w9 gnd d12 gnd j14 gnd t3 pf14 b7 tmr1 l2 data4 y8 gnd d13 gnd k7 gnd u3 pf15 a7 tmr2 k2 data5 w8 gnd d14 gnd k8 gnd v2 ppi_clk a4 tms u2 data6 y7 gnd d18 gnd k9 gnd v3 ppi0 a5 trst u1 data7 w7 gnd e3 gnd k10 gnd v6 ppi1 b5 tsclk0 p1
ADSP-BF539 / ADSP-BF539f rev. f | page 59 of 60 | october 2013 outline dimensions dimensions in the outline dimensions figures are shown in millimeters. surface-mount design table 46 is provided as an aid to pcb design. for industry- standard design recommendations, refer to ipc-7351, generic requirements for surfac e mount design and land pat- tern standard . figure 59. 316-ball chip scale package ball grid array [csp_bga] (bc-316-2) dimensions shown in millimeters compliant to jedec standards mo-275-mmab-1. with exception to ball diameter. 0.80 bsc a b c d e f g h j k l m n p r t v w u y 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 17 18 19 20 15.20 bsc sq 0.50 0.45 0.40 0.35 nom 0.30 min 17.10 17.00 sq 16.90 coplanarity 0.20 bottom view detail a top view ball diameter seating plane 1.70 max a1 ball corner a1 ball corner detail a 1.08 1.01 0.94 table 46. bga data for use with surface-mount design package package ball attach type package solder mask opening package ball pad size 316-ball csp_bga (bc-316-2) solder mask defined 0.40 mm diameter 0.50 mm diameter
rev. f | page 60 of 60 | october 2013 ADSP-BF539 / ADSP-BF539f ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06699-0-10/13(f) ordering guide the models shown in the following table are available with con- trolled manufacturing to support the quality and reliability requirements of automotive applications. note that these auto- motive models may have specifications that differ from the commercial models and designers should review the product specifications section of this data sheet carefully. contact your local adi account representative for specific product ordering information and to obtain the specific automotive reliability reports for these models. model 1 temperature range 2 instruction rate (max) flash memory package description package option adbf539wbbcz4xx C40c to +85c 400 mhz n/a 316-ball csp_bga bc-316-2 adbf539wbbcz5xx C40c to +85c 533 mhz n/a 316-ball csp_bga bc-316-2 adbf539wbbcz4f8xx C40c to +85c 400 mhz 8m bit 316-ball csp_bga bc-316-2 adbf539wbbcz5f8xx C40c to +85c 533 mhz 8m bit 316-ball csp_bga bc-316-2 1 z = rohs compliant part. 2 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see operating conditions on page 26 for junction temperature (t j ) specification which is the on ly temperature specification.

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